- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi,
We are facing an issue in simualtions, with the data transmitted from PCIe hard-IP model during initialization while switching from Gen1 to Gen3 Speed. The model being used is the one for A10 FPGA device. Here’s the issue:
After moving Recovery.Speed state and sending TS ordered set, HIP is sending unknown symbols on Tx with HiZ on the lines.
The said behavior is seen repeatedly for a long time before HIP Tx enters electrical Idle.
The simulation has enabled fast_sims in serial mode.
Appreciate help/suggestions
Thanks,
RamaMohan
- Tags:
- PCIe
Link Copied
- « Previous
-
- 1
- 2
- Next »
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hie RamaMohan,
I believe my last update did not get through.
I tried with VCS and still unable to reproduce the issue. Hence, without your RP BFM, I am unable to replicate the failure and de bug further.
Regards,
Nathan
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page
- « Previous
-
- 1
- 2
- Next »