Issue with PCIe HIP(A10) Gen3 model behavior in simulations with serial interface

[RamaMohan]

Hi,

We are facing an issue in simualtions, with the data transmitted from PCIe hard-IP model during initialization while switching from Gen1 to Gen3 Speed. The model being used is the one for A10 FPGA device. Here’s the issue:

After moving Recovery.Speed state and sending TS ordered set, HIP is sending unknown symbols on Tx with HiZ on the lines.

The said behavior is seen repeatedly for a long time before HIP Tx enters electrical Idle.

The simulation has enabled fast_sims in serial mode.

Appreciate help/suggestions

Thanks,

RamaMohan

[RamaMohan]

Hi Nathan, Appreciate if you can get this issue reproduced and get the fix ASAP. This is really blocking us. Thanks, RamaMohan

[Nathan_R_Intel]

​Hie  RamaMohan,

I believe my last update did not get through.

I tried with VCS and still unable to reproduce the issue. Hence, without your RP BFM, I am unable to replicate the failure and de bug further.

Regards,

Nathan