JESD IP core: Same link clock shared between all transciever lanes

[Altera_Forum]

Hi All, 

 Is it possible to use a common external reference clock for L lanes transceivers in JESD 204 IP core??or do we need separate external reference clock for each sets of lane??  Thanks in advance. CG6991

[Altera_Forum]

--- Quote Start ---   Is it possible to use a common external reference clock for L lanes transceivers in JESD 204 IP core??or do we need separate external reference clock for each sets of lane??   --- Quote End ---    Did you look at the JESD204B standard?  http://www.jedec.org/sites/default/files/docs/jesd204b.pdf  (You have to register, but the standard is free)  The links are encoded, so in general you could create a system with reference oscillators, and allow the clock-and-data recovery unit to track any phase/frequency-shifts between those oscillators, just as you would in a network setup. However, if you are using multiple ADCs, and those ADCs are synchronous, then its just as easy to use a common reference clock for all the ADCs and FPGAs.  Analog Devices has an article on JESD204B  http://www.analog.com/static/imported-files/tech_articles/jesd204b-survival-guide.pdf  What are you trying to do?  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  Did you look at the JESD204B standard?  http://www.jedec.org/sites/default/files/docs/jesd204b.pdf  (You have to register, but the standard is free)  The links are encoded, so in general you could create a system with reference oscillators, and allow the clock-and-data recovery unit to track any phase/frequency-shifts between those oscillators, just as you would in a network setup. However, if you are using multiple ADCs, and those ADCs are synchronous, then its just as easy to use a common reference clock for all the ADCs and FPGAs.  Analog Devices has an article on JESD204B  http://www.analog.com/static/imported-files/tech_articles/jesd204b-survival-guide.pdf  What are you trying to do?  Cheers, Dave  --- Quote End ---    Hi Dave, Thanks for the info I am actually interfacing multiple synchronous ADCs through JESD with Arria V GZ and would like to know if one common reference clock pin is enough in the FPGA side for the all the Lanes. We know that for L transceiver channels in the FPGA side we have L/3 exteranl reference clock pins dedicated. Hence I would like to know if we could only one of the external reference clock pin can be used for all the channel PLLs(transceivers).  Thanks in advance, Gowtham

[Altera_Forum]

Hi Gowtham, 

  --- Quote Start ---   I am actually interfacing multiple synchronous ADCs through JESD with Arria V GZ and would like to know if one common reference clock pin is enough in the FPGA side for the all the Lanes. We know that for L transceiver channels in the FPGA side we have L/3 external reference clock pins dedicated. Hence I would like to know if we could only one of the external reference clock pin can be used for all the channel PLLs(transceivers).   --- Quote End ---   Given that the ADCs are synchronous, then yes, a single reference clock at the FPGA should be sufficient. However, you should synthesize an example design to make sure that the FPGA clock pin you select is acceptable. For example, I have run tests where REFCLK inputs on the left-side of a device are not acceptable to transceiver blocks on the right-side of the device, so in that case, I have explicitly designed the boards with external clock fanout ICs and made the FPGA REFCLK inputs programmable via those external devices (SiLabs and TI have parts that are specified for 10Gbps performance).  So, the only answer you should accept in this regard is the answer provided by Quartus :)  Which Arria V GZ board are you using? TI have an FMC development kit  http://www.ti.com/tool/tsw14j56evm  That I am using now. I can give you a basic top-level example design that includes the DDR interface. I'm just starting to work with the transceiver IP now. Once I have that working, I'll look at the JESD204B IP cores. I will then test the ADS42JB69EVM.  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  Hi Gowtham,  Given that the ADCs are synchronous, then yes, a single reference clock at the FPGA should be sufficient. However, you should synthesize an example design to make sure that the FPGA clock pin you select is acceptable. For example, I have run tests where REFCLK inputs on the left-side of a device are not acceptable to transceiver blocks on the right-side of the device, so in that case, I have explicitly designed the boards with external clock fanout ICs and made the FPGA REFCLK inputs programmable via those external devices (SiLabs and TI have parts that are specified for 10Gbps performance).  So, the only answer you should accept in this regard is the answer provided by Quartus :)  Which Arria V GZ board are you using? TI have an FMC development kit  http://www.ti.com/tool/tsw14j56evm  That I am using now. I can give you a basic top-level example design that includes the DDR interface. I'm just starting to work with the transceiver IP now. Once I have that working, I'll look at the JESD204B IP cores. I will then test the ADS42JB69EVM.  Cheers, Dave  --- Quote End ---    Hi Dave,  Thanks for the info. I am doing a study about Arria V GZ transceivers and JESD IP core in the same tsw14j56evm.  Thanks, Gowtham

[Altera_Forum]

Hi Gowtham, 

  --- Quote Start ---   Thanks for the info. I am doing a study about Arria V GZ transceivers and JESD IP core in the same tsw14j56evm.   --- Quote End ---   Great!  Have you tested any of the JESD204B IP yet? I have not. I first wanted to start with some simple transceiver based designs, and then see if I can interface to the JESD204B links directly, and create my own (free) IP.  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  Hi Gowtham,  Great!  Have you tested any of the JESD204B IP yet? I have not. I first wanted to start with some simple transceiver based designs, and then see if I can interface to the JESD204B links directly, and create my own (free) IP.  Cheers, Dave  --- Quote End ---    Hi Dave,  Sorry for the late reply. Regarding JESD204B IP i have also not yet tested any. I am actually working on dynamic reconfiguration of the transport layer IP provided by Altera.  Thanks, Gowtham