Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Altera_Forum
Honored Contributor I
1,693 Views

JESD204B device clk

Hi! 

 

My task is to develop and debug JESD204B based measurement system. 

I have a DEV-ADC34J22 board connected to Cyclone V GT development kit through HSMC connector. 

The adc board has HSMC_CLK (device clk for jesd204b core) net from the clock management IC LMK04828B routed to HSMC connector (pins 14,16 see ADC_DEV_KIT_SCH_Page2_device_clk.png). 

The CVGT board doesn't have such a connection (CVGT_DEV_KIT_HSMC_Page18.png). 

 

Both of the boards have the differential clock net SPARE_CLK (HSMC pin 156, 158 see ADC_DEV_KIT_SCH_Page3_spare_clk.png) what I tried to use as a JESD device clk input  

(instead of missing HSMC_CLK) to the Cyclone V GT FPGA (PIN_H17 and PIN_H16).  

What resulted to the fitter error (see fitter_err___HSMA_CLK_IN_P2_PIN___H17.png). 

 

Is there any possibility to use SPARE_CLK net or some similar one routed to the HSMC connector for driving JESD IP CORE device clk input in Cyclone V GT?
0 Kudos
8 Replies
Altera_Forum
Honored Contributor I
49 Views

I have a similar issue with the Stratix V dev-kit in which I want to connect 12 JESD lines and there are only 12 XCVRs available and none of the dedicated reference clocks are routed out to HSMC connectors. I spent a while looking over the documentation and found that it is actually possible to use standard clock inputs for the high speed transceivers. So far I have only test compiled my design and it fits successfully - still waiting on PCBs before I can actually test it. With that I mind I thought I would selfishly help you in the hope you can test it out and let me know if the following works for you. 

 

The XCVRs have three possible clock sources. In order of preference, they are: (1) dedicated XCVR refclk inputs (non broken out). (2) spare XCVR RX channels (doesn't help either of us). (3) the output of an FPLL. 

 

Option (3) may be the saviour in both our designs. It is possible to use the output of a fractional PLL in the PLL Strip to clock the transceivers. The FPLL can in turn use a standard clock input as its reference clock. This is a bit of an obscure way to do it, but should work. 

 

Looking at the CV datasheet, for your device it appears there is indeed a PLL strip which will help. Specifically FRACTIONALPLL_X0_Y64 and FRACTIONALPLL_X0_Y81 can both be clocked from the dedicated reference clock inputs on HSMC_A_CLK_IN_1, HSMC_A_CLK_IN_2, and HSMC_B_CLK_IN_2. This is good because it means there is a way to get the spare clocks into the FPLLs and hence into the XCVRs. 

 

My suggestion looking at the CV dev kit is for you to use the HSMC *B* connector. The reason for this is it means all of the XCVRs are grouped together which will make life easier (both in terms of timing, and fitting). If you connect to HSMC B, and then use the spare device clock, I believe pins J20 and K19. This will bring in your device clock. Next, instantiate a fractional PLL which uses this clock as the input, and then produces 3 output clocks, the two you need anyway for the JESD core (frame clock and link clock), and a third which is the same frequency as the input clock which you will feed as the device clock to the JESD core. 

 

With these connections the fitter should be able to map the design into either of the two FPLL locations I mentioned above. 

 

--- 

 

As I say, if you can try this out and let me know if it works, that would be great.
Altera_Forum
Honored Contributor I
49 Views

For more info, you can consult the Cyclone V handbook vol. 2 here: https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/cyclone-v/cv_5v3.pdf 

 

The table on P63/P64 (Table 2-1) shows the clock sources for the transceivers. Note that for JESD we need the CDR blocks, so you need a clock source that says 'Yes' in that column of which only the three I identified above are available. 

 

If you scroll down a bit to the bottom of P66, it explains using the FPLL as a clock source.
Altera_Forum
Honored Contributor I
49 Views

Hi! 

 

That does work! I must confess I tried to use fPLL but my mistake was to use fPLL as a buffer for routing device clk from input FPGA pin to feed JESD core pll. 

Now I set one fPLL as JESD core PLL according to your advice and it works! 

 

The one thing I have not realized at the moment - why did you advice me to use HSMC_B more than HSMC_A? HSMC_A has the same number of receiver pairs as HSMC_B and I compiled the project for HSMC_A and device clk pin H17, H16. 

 

Thanks in advance for your help!
Altera_Forum
Honored Contributor I
49 Views

If you look at the transceiver pin assignments, the ones for HSMCA seem to be all over the place, and are mixed in and around the PCIe ones. Whereas the HSMC B ones are fairly well grouped. It's probably better in terms of jitter performance to have them all nearby. But also if you want to add PCIe stuff to your design (don't know if you are), then there may be fitting problems. Not sure, just a thought. If HSMCA works for you, use that one.

Altera_Forum
Honored Contributor I
49 Views

I've understood! I am really going to add PCIe module in the design. But I need to start up the JESD one at first.  

 

Thank you a lot for your advice!!!
Altera_Forum
Honored Contributor I
49 Views

Hi all, I have a question regarding DEV-ADC34j22. How can I interface this Board with DE2-115 Altera? 

Is it possible? Both are using HSMC connector but how can I find this pin assignment? 

 

Regards
Altera_Forum
Honored Contributor I
49 Views

@rebk There will be pin assignments in the DE2-115 reference manual, and pin assignments for the DEV-ADC34J22 dev kit in its manual. Compare them both.

Altera_Forum
Honored Contributor I
49 Views

TCWORLD, 

 

Thanks. Is there any demonstration project for this DEV-ADC34j22 with any Altera Development board just to get idea about the whole process for AD converting?
Reply