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Altera_Forum
Honored Contributor I
735 Views

Logic Analyzer Interface (LAI) destroys my design

Hi everyone! 

 

I have the following problem: 

I made a design with PCIe, I²C, SPI and a SRAM-Memory. 

The I²C- and SPI-Cores are made by myself and connected to the PCIe HIP with some PIOs. The SRAM is connected via the Generic Tri-State Controller in QSYS. 

Now I wanted to use the LAI to route some signals to a debug-port to check them in an oszilloscope. 

But everytime I implement the LAI into my design, the I²C- and SPI-PIOs show wrong Values and after a few reads (with "pci_debug") on them my whole Computer (Debian) crashes so I have to do a hard power off. 

This doesn't happen if I read on the SRAM. I can even measure the signals of the SRAM on the Debug-Port. 

 

Are there any known issues with the LAI? 

 

I use Quartus 12.1 SP 1.33
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3 Replies
Altera_Forum
Honored Contributor I
36 Views

Did you run the timing analyzer when you built the design. Were there any failing paths?

Altera_Forum
Honored Contributor I
36 Views

Yippeeeee! 

That was the right pointer! Thank you Tricky! 

 

I had no .sdc file in my design. I played a bit with the Timing Analyzer and generated a .sdc and now it works! 

 

Sometimes you only have to make the right question. 

OK, but there are a lot red enties in the Timing Analyzer reports. Don't know what to do with all that. And besides, my design works fine (for now). 

 

Thank you again!
Altera_Forum
Honored Contributor I
36 Views

Red paths are the ones that dont meet the timing specs specified. Usually this means investigating and adding more pipelining or doing some other funky constraining (but the pipelining is usually the easiest).

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