This is the MAX10 reference design - this was modified from what is posted on the design store that does not run:
The TEST_MAC_LB 1000M and TEST_MAC_PHY_LB 1000M tests run successfully. 1G and 10/100 were tested.
The source files were moved around so they are not in generated directories which is not a good idea. The PLL and SDC timing was corrected. The design passes timing now.
The PHY setup was also corrected. The original had the PLL phase shifted the TX clock and the TCL scripts told the PHY to phase shift. So the data was changing at the same time it was being captured.
The TCL scripts were missing in the V18 download. They were pulled from the original Quartus version 15 download and added to the zip. The attachment is a zip of the design dir.
The TCL scripts have a while loop that looks for status that isn’t necessary. So there is a long delay that seems to be needless but I didn’t change it just in case there is a reason for it.
This work was done by Scott Prigmore of the embedded cluster.
For more complete information about compiler optimizations, see our Optimization Notice.