MCDMA example design Modelsim Simulation failing for Agilex

[SLabe]

Hi, when following the steps in UG for MCDMA example design in Quartus PE 21.1, I get the following error in Modelsim.

# ** Error: (vsim-3033) Instantiation of 'ctp_tile_encrypted' failed. The design unit was not found.
# Time: 0 ps Iteration: 0 Instance: /pcie_ed_tb/pcie_ed_inst/dut/dut/ast/inst/inst/maib_and_tile/z1565a File: $MODEL_TECH/../altera/verilog/src/ctp_hssi_atoms.sv Line: 39100

The rest of the design appears to compile correctly and error free.

I'm using Windows 10.

[RichardTanSY_Intel]

May I know which MCDMA example design that you are referring to ? Which UG?
Kindly help to clarify on this so that we are aligned. 

The error is saying that ModelSim can't find this design unit. There could be something wrong with the instantiation of the "ctp_tile_encrypted" module in ctp_hssi_atoms.sv file. You may need to check on this.

[SLabe]

@RichardTanSY_Intel , were you able to reproduce my error? I did see online that simulation for MCDMA P-Tile PCIe may only be supported by Modelsim SE, PE and Questa from Mentor. Could this be the issue? If so, will the new Questa Intel FPGA Edition Beta work? (I'm waiting on a license to try)

https://www.intel.com/content/www/us/en/programmable/documentation/xzr1589413426034.html#cot1589416902981

Thank you!

[SLabe]

I just tried the new Questa Intel FPGA Edition. Same error:

# Start time: 14:30:55 on May 13,2021
# ** Note: (vsim-3812) Design is being optimized...
# ** Error: $MODEL_TECH/../intel/verilog/src/ctp_hssi_atoms.sv(39100): Module 'ctp_tile_encrypted' is not defined.
# For instance 'ctp_tile_encrypted_inst' at path 'pcie_ed_tb.pcie_ed_inst.dut.dut.ast.inst.inst.maib_and_tile.z1565a'
# ** Error: $MODEL_TECH/../intel/verilog/src/ctp_hssi_atoms.sv(39100): Module 'ctp_tile_encrypted' is not defined.
# For instance 'ctp_tile_encrypted_inst' at path 'pcie_ed_tb.dut_pcie_tb.dut_pcie_tb.g_bfm.p_dut_ep.altpcietb_bfm_top_rp.g_bfm.u1.rp.inst.dut.inst.inst.maib_and_tile.z1565a'
# Optimization failed
# ** Note: (vsim-12126) Error and warning message counts have been restored: Errors=2, Warnings=0.
# Error loading design

[SLabe]

Hi I'm using the following section of the UG for running the simulation:

https://www.intel.com/content/www/us/en/programmable/documentation/nki1590181067003.html#pkj1592875121012

I do know the guide is out of date and an update is coming for 21.1...

In Quartus 21.1 I generate the example design for Multi Channel DMA P-Tile for PCI Express everything left as is targeting the Agilex F-Series P-Tile ES0 development kit. I've tried with both "PIO using MQDMA  Bypass mode" and "AVMM DMA" examples. 

One final note, I use ModelSim FPGA Edition for simulation.

Thank you,

[BigHandsomeBee]

Same error for Stratix 10 DX.

[RichardTanSY_Intel]

Hi @BigHandsomeBee 

There seems to be an issue with the previous Quartus version when generating example design, Modelsim Intel Edition and Questa Intel Edition will not able to simulate it. 

The workaround is to simulate it using third party simulator Modelsim SE and QuestaSim. 

You may checkout the documentation here for supported simulators:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug20303.pdf

Or you can download the latest Quartus version 21.2 in which we have fix the issue and simulate it using the Modelsim Intel Edition and Questa Intel Edition.

Let me know if it works. 

Best Regards,
Richard Tan

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos. 

[RichardTanSY_Intel]

With the solution provided, I will now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Best Regards,
Richard Tan

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.