FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5982 Discussions

Max 10 ADC simulation problem

Altera_Forum
Honored Contributor II
1,031 Views

I am generating an ADC core only, and I am trying to get the simulation in modelSim using the gui. I generated the ADC in verilog, and I added all the support files in the submodules dir. It compiles OK, but when I try to load the design, it gives an error:  

** Error (suppressible): (vsim-10000) C:/Project/Repository/Other Projects/SenseSole/FPGA/FPGA_Code_RevAQ15/ADC_Core/simulation/submodules/altera_modular_adc_control_avrg_fifo.v(93): Unresolved defparam reference to 'scfifo_component' in scfifo_component.add_ram_output_register. 

 

There is scfifo but no scfifo_component. Can anyone tell me how to fix this, and thank you in advance.
0 Kudos
1 Reply
Altera_Forum
Honored Contributor II
124 Views

Try using the auto-generated script for setting up ADC simulation 

 

It is generated from Qsys under directory  

 

<myip>/simulation/mentor/msim_setup.tcl 

 

Follow steps as below. 

1. Open Modelsim Navigate to location of scripts. 

2. do msim_setup.tcl 

3. ld_debug 

 

For further reading. 

https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_intro_to_megafuncti... 

Topic 1.6 Simulating Intel FPGA IP Cores 

 

Best Regards, 

arslanusman2003 

(This message was posted on behalf of Intel Corporation)
Reply