I am generating an ADC core only, and I am trying to get the simulation in modelSim using the gui. I generated the ADC in verilog, and I added all the support files in the submodules dir. It compiles OK, but when I try to load the design, it gives an error:** Error (suppressible): (vsim-10000) C:/Project/Repository/Other Projects/SenseSole/FPGA/FPGA_Code_RevAQ15/ADC_Core/simulation/submodules/altera_modular_adc_control_avrg_fifo.v(93): Unresolved defparam reference to 'scfifo_component' in scfifo_component.add_ram_output_register. There is scfifo but no scfifo_component. Can anyone tell me how to fix this, and thank you in advance.
Try using the auto-generated script for setting up ADC simulationIt is generated from Qsys under directory <myip>/simulation/mentor/msim_setup.tcl Follow steps as below. 1. Open Modelsim Navigate to location of scripts. 2. do msim_setup.tcl 3. ld_debug For further reading. https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_intro_to_megafuncti... Topic 1.6 Simulating Intel FPGA IP Cores Best Regards, arslanusman2003 (This message was posted on behalf of Intel Corporation)