For DDR4 memory there is a limitation on operating frequency which is 300Mhz and emif ip has maximum data width upto 144 bits. Are there other methods to increase the data rate?
What you are asking is the supported EMIF spec for Arria 10 FPGA. The EMIF spec will vary accordingly depends on user selected EMIF configuration setting.
For instance, Arria 10 EMIF DDR4 IP can support
You can find EMIF IP different configuration setting supported spec in below link
If one DDR4 IP interface bandwidth is not sufficient to support your design application need then you can consider to use 2 DDR4 IP interface or more