09-18-2012 03:44 AM
Hi,I'm having a problem driving different blocks of my design with different clock rates. Suppose I want the following system: Input Signal (50 MSPS) --> CIC Filter (decimate by 25) --> FIR Filter (2 MSPS) The base clock of the design is 50 MHz. The input signal is sampled at the base rate, 50 MSPS, then the CIC decimates the signal to 2 MSPS. How do I get the FIR filter to operate at 2 MSPS? I cannot access the clk input to the FIR filter and force it to operate at a slower clock rate. The FIR seems to tied to the base clock and outputs at the fast rate. The CIC filter and FIR filters are implemented using Megacore functions from the Altera Standard Blockset. I've changed the filter sampling frequency in the coefficient definition to the appropriate rate (2 MHz). I've also attached a figure to highlight the issue. An impulse is applied to the FIR under two conditions: 1. An impulse with sample time of 1/50e6 seconds. The expected impulse response of the FIR filter is shown. 2. An impulse with sample time of 1/50e6 * 25 seconds. The impulse response of the FIR filter is as if a pulse of 25 samples at 50MSPS were applied. Thanks for help!!
09-18-2012 06:28 AM
--- Quote Start --- I cannot access the clk input to the FIR filter and force it to operate at a slower clock rate. The FIR seems to tied to the base clock and outputs at the fast rate. --- Quote End --- Why not reading the FIR compiler handbook? The FIR filter has sink_valid to command the input data rate. Simply wire it to CIC dout_valid. Operating the FIR filter with multiple clock cycles per sample offers the option to save resources by selecting a serial or multibit serial topolgy.
09-18-2012 05:05 PM
Thanks for the response. I was not aware that the sink_valid input controls the FIR clock rate.In the example with the impulse response, how would I tied the sink_valid signal to let the FIR know the input pulse is coming at 2 MSPS? Since the data is valid at the start of the pulse. There's no difference between that and the pulse at 50MSPS. Thanks!
09-18-2012 07:27 PM
The compare conditions in post# 1 aren't exactly clear to me. Do you run the same filter h(n) with different sample rates?In a realistic testbench, the filter should be calculated for 2 MSPS input rate, sink_valid supplied with a 2 MHz clock enable and the test signal clocked at the same rate.