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Multi-port Front End Reference Design- Simulation fails in Quartus 14.0V

Honored Contributor II


I"m using Quartus 14.0v and I'm trying to simulate the MPFE reference design provided by Altera in Q14.0 but it fails.  

The reference design used "Quartus II version 10.1 and ModelSim version 6.6a", does it creates any problem with Quartus 14.0 and Modelsim 10.1e version. 


** Error: Vsim ALTERA is incompatible with D:/../../../MPFE_Reference_Design/design_example/my_qsys_mpfe_system/sim_verilog/verilog_libs/altera_mf_ver/scfifo/_primary.dat file.# ** Fatal: Bad library format, library not compiled with ALTERA compiler.# Time: 0 ps Iteration: 0 Instance: /my_qsys_mpfe_system_tb/u0/uniphy_ddr3/controller_phy_inst/alt_ddrx_controller_inst/input_if_inst/wdata_fifo_inst File: ./submodules/altera_uniphy_ddr3_nzhdlyea_alt_ddrx_wdata_fifo.v# FATAL ERROR while loading design# Error loading design 



What could be the reason..?? How to solve this Issue..?? 



thanks and regards 

Vinod Kumar
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Honored Contributor II

IP and reference models often need to run on the same version they were generated with. I suggest dropping down to q10.1 and modelsim 6.6

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