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Altera_Forum
Honored Contributor I
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Cyclone V + Jesd + Transceiver Debug

Hi All! 

 

I develop a JESD204B (subclass1) based system. 

I use Cyclone V GT, Terasic DE1 and ADC board http://dallaslogic.com/prod_dev-adc34j/  

 

Firstly, I developed an Altera JESD IP Core based system. 

But then I created a simplier system with one Custom PHY Transceiver core, reconfiguration controller and try to get initial synchronization data from it (K28.5 from ADC) debugging it in Signal Tap. 

 

I assert and deassert reset of the Transceiver's Core PLL from NiosII via pio at the beginning after ADC initialization, and then get the Transceiver core locked to ref and data state. It means that core detects the serial bit stream from ADC and gets synchronized with it. 

 

But the data on the parallel port of the core is far from 0xBC (K28.5) and I can't understand what it represents itself as well is it real data from the detected bit stream or some wrong unresetted value(?). 

 

The question is: 

 

Do I need to control the Custom Transceiver PHY from NiosII and do some special adjustments, or the initial mgmt hardware reset of the PHY & reconfig controller is the enough condition for proper core operation?
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