Hello,I am trying to implement two memory controllers (dual channel) in Stratix IV device. FPGA have enough resources for two controllers so I don't need to share the DLL or PLLs. I have duplicated all the modules and modified pin assignments. I am getting some critical and non-critical warnings like: Critical Warning: PLL clock b_ddr2hpc_inst|ddr2hpc_controller_phy_inst|ddr2hpc_phy_inst|ddr2hpc_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL. Warning: ddr2hpc_phy_ddr_timing.sdc: Failed to find PLL input clock pin driving b_ddr2hpc_inst|ddr2hpc_controller_phy_inst|ddr2hpc_phy_inst|ddr2hpc_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk I have two different dedicated reference clocks for each PLL still I get the same critical warning. When I load the design into FPGA, it doesn't work. Is there anyone got multiple memory interfaces working using MegaWizard Plug-in based flow? I appreciate any kind of help or ideas about what might be missing or wrong. Thanks
Hello,I have narrowed down the problem. My FPGA (StratixIV GX 530) has two DRAM channels. I am using DDR2 High Performance Controller and I have DDR2-800 SODIMMs. When I use the channel A for my I/O everything works fine. When I switch the I/O pins to the channel B, I got the errors above. Everything is same except the pin assignments for my memory controller. For channel B design I am sure that I have the correct pin assignments. Since it complains about the clock input to PLL I tried couple other clock inputs with 1.8V I/O standard. Still same issue. Any ideas?
Hi,I found a hack as a workaround since I had exactly the same problem with the Terasic DE4 board (Stratix IV GX 230), channel 1 works but channel 2 had that same critical warning. The DE4 board has several dedicated clock pins distributed among different banks, so DRAM channel 1 which has pins on the bottom edge of the board should use a bottom PLL so it needs a clock pin in one of the bottom banks. It turns out that there is only 1 dedicated PLL input pin in the top banks where DRAM channel 2 has its pins and it was not the one that the templates from Terasic suggested. This is where some hacking comes in: Take a look at the pin planner for your device, find all the clock pins that are in the same I/O banks as where DRAM channel 2 has its pins. I'm using Quartus 9.1 and clock pins have a round icon that inside has what looks like a rising edge waveform (some also have a falling edge). Using a self-made blinking LED test (takes like 15 minutes to put together), I found out which clock pins are actually connected to the board's oscillators and which are dedicated PLL clock input pins (after compiling check the warnings in Quartus so see whether each clock pin got a node promotion to a global clock, or some similar warning). Currently preliminary experiments are working, both channels operate at 400 MHz but channel 1 uses a 50 MHz input (OSC_50_BANK3, PIN_AV22 in my case) and channel 2 uses a 100 MHz input (GCLKIN, PIN_A21 in my case), so I have 2 separate mega-wizard generations each instantiated once. Good luck and have fun, Jason