FPGA Intellectual Property

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FPGA Intellectual Property

Discussions

8K SDI Signal Pattern Generator

3g-sdi test pattern generator

Video synchronism signals on DisplayPort

to use altlvds,how I can use LVDS bit clock and LVDS frame clock of ADC at the same t

max burst size

PB with Customer peripheral

Issue about DMA Read with PCIe Hard IP (for ARRIA10) in simulation

Bug in Altera LDPC Encoder, problem with flow control

ethernet ip

JESD204B device clk

8E1111 PHY tx_clk and rx_clk

Is there any way to initialize onchip-ram with auto-generated data instead of an .mif

Error reported by S-function 'mip_control' in Control Block

Using UART at arbitrary BAUD Rate

SRIO IP core with loop simulation

Featured Content

Agilex 5 MCDMA Example Design Identification Issues

Arria 10 PCIe Gen 3 stuck at Equalization.Phase3

PCIe with DMA Memory Sizing