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5878 Discussions

NCO IP output is shifting wrt output valid on aria10 eval board

dinkersemwal
Novice
492 Views

Hi All,

I am using intel NCO IP as DDS to generate a LO for the mixer.

when i am testing my module on board(aria10 eval), i observe that output sample is shifting by one clock (back and forth with each reboot) wrt valid. 

this is not observed in the simulation

*output valid comes at fixed latency wrt clken, (10 clks).

this is not observed in the simulation.

iam not able to understand this behavior of IP.

what could be the issue? please suggest.

Thanks.


IP parameters are as follows:

clk =245.76 MHz.

architecture = multiplier based

no of band =1

no of ch =1

clock cyc/output =1

phase acc =18bit

ang resolution =18bit

mag resolution = 16bit

freq mod and phase mod= disabled.

dithering = disabled.

0 Kudos
1 Solution
SengKok_L_Intel
Moderator
404 Views

Hi,

This might be related to the reset, you probably need to hold the reset for a few clock cycles while the clken is asserted.


Regards -SK


View solution in original post

8 Replies
SengKok_L_Intel
Moderator
480 Views

Hi,


Did you reset the NCO IP after power up? Does the behavior change after each reset?


In order to better understand the problem, it will be helpful if you can attach the waveform of your simulation and hardware result.


Regards -SK


dinkersemwal
Novice
459 Views

Hi SK,

thanks for the response.

This behavior is not very consistent it is coming once in very 8 to 10 reboots.

and output is not just one sample shifted but samples are totally different some times. 

Did you reset the NCO IP after power up? Does the behavior change after each reset?

>>Yes NCO gets reset after Power up, but behavior doesn't change at every reset.  it changes after reboot.

i am attaching the simulation and the signal tap wave form.

simulation captures expected samples .

and signal tap capture change in the behavior 

Thanks

Dinker

 

SengKok_L_Intel
Moderator
449 Views

Hi,


Do you reset the NCO IP after the input clock of NCO is stable? When the problem happens, if you issue a reset, does it remain the same?


Regards -SK


dinkersemwal
Novice
419 Views

Hi SK

Do you reset the NCO IP after the input clock of NCO is stable? When the problem happens, if you issue a reset, does it remain the same?

>>once clock is stable and module reset is de asserted, i am not resetting the NCO again.

but in simulation i observed that when i force reset in between the behavior is same as observed on board.

 

thanks & Regards

Dinker

SengKok_L_Intel
Moderator
405 Views

Hi,

This might be related to the reset, you probably need to hold the reset for a few clock cycles while the clken is asserted.


Regards -SK


dinkersemwal
Novice
388 Views

Hi SK,

Thanks for the reply.

>>This might be related to the reset, you probably need to hold the reset for a few clock cycles while the clken is asserted.

yes, i also feel the same . even data diagram in IP document shows the same. 

dinkersemwal_1-1615824424310.png

 

In my design reset is de asserted long before clken. clken is asserted when i get IQ_in valid. 

what if, i reset NCO IP again after the clken is asserted?

I have one concern, that what will happen if NCO ip gets a synchronous reset? (its aspects asynchronous reset).

Thanks.

Regards

Dinker

 

 

 

SengKok_L_Intel
Moderator
367 Views

In the user guide, it states the reset is asyn, however, based on the waveform, the reset is de-asserted during the clk_en is asserted.


SengKok_L_Intel
Moderator
324 Views

If further support is needed in this thread, please post a response within 15 days. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions. 


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