FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5986 Discussions

Need some advices on designing multiple DMA in a PCIE bridge chip

Altera_Forum
Honored Contributor II
751 Views

Hi everyone, 

 

I'm now starting to do a PCIE bridge with video and audio DMA. 

 

My final goal is to have 4 video interfaces (BT1120) and at least 4 audio interfaces (I2S) as the data input of this bridge. 

For now, only one video interface and one audio interface have been done in my design as a preliminary test. 

 

For the video part, I have the following design for DMA transfer from BT1120 to allocated memory on PC. 

Clocked video input IP --------> DMA writer from mSGDMA --------> txs port in PCIE HIP 

 

For the audio part, I write a module named "I2S module" to convert I2S to avalon st.  

The design for DMA transfer from I2S to allocated memory on PC looks like: 

I2S module --------> FIFO --------> DMA writer from mSGDMA --------> txs port in PCIE HIP 

 

Now, here comes my three questions: 

 

1. Multiple DMA arbitration problem: 

If I enable both video and audio DMA and the input video is 1080p60, how do I ensure the video DMA can generate 60 interrupts in a second? 

From what I understand, this is a multiple master to one slave design on avalon mm bus and interconnection fabric should do the arbitration automatically. Can I assign a higher priority to the video DMA part? 

 

2. Resource sharing problem: 

For my current design, each video or audio interface requires a DMA writer and a DMA dispatcher. 

Therefore, in order to achieve my final spec, my design will need at least 8 DMA writers and 8 DMA dispatchers. 

It's kind of waste because these 8 DMA writers and 8 DMA dispatchers cannot work at the same time. 

It would be better if my design becomes as follows: 

Clocked video input IP--> MUX --> DMA writer from mSGDMA --> txs port in PCIE HIP 

I2S module ---> FIFO ---> 

 

The selection signal of MUX may come from some sort of priority arbitrator circuits. 

For this kind of design, how should I do to avoid data loss? Increase the size of FIFO? Add a FIFO after clocked video input IP? 

 

3. FIFO size: 

Is there a good way to decide the required size of FIFO? 

For now, I just use try & error to find a suitable size of the FIFO. 

 

Any advice and idea are welcome to my questions. Thanks.
0 Kudos
0 Replies
Reply