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Nios II Processor does not work correctly when integration into existing FPGA design

Altera_Forum
Honored Contributor II
719 Views

Hi, 

 

I have a huge problem when i try to integrate the Nios II/e processor into an existing FPGA Design.  

Im using an Cyclone IV EP4CE6E22C8N /50 MHz development kit. 

 

When i build / generate and run the Processor as a "standalone" it works absolutely fine (debug output / digital outputs / timings). 

 

But when i try to integrate it into an existing design it seems that the base adresses get mixed up and the processor does not work. 

In Eclipse IDE it says that the flash process works fine and the processor starts but the debug outputs wont and digital outputs do not work. 

I tried to generate the BSP new but without any success.
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2 Replies
Altera_Forum
Honored Contributor II
63 Views

Could you post your project?

Altera_Forum
Honored Contributor II
63 Views

Hi! 

After going through every line of code and qsys i found the mistake... Was (like every time) a very simple one 

 

Thanks for helping!
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