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PCI Express Hard IP Avalon-MM legacy interrupt handling




I would like to interrupt a PCI express root port from inside the FPGA through Avalon-MM bridge as an endpoint.


Internally a level based interupt signal is generated that should generate an interrupt all the way to the PCI express root port.


I have read a lot about different interrupt solutions supported in Cyclone V Avalon-MM Interface for PCIe Solutions (ug_c5_pcie_avmm).


I know I need to interface the CRA slave module to configure interrupts.

My first idea is to use the legacy interrupt solution through the Avalon-MM Rx Master interface (RXirq_irq(15:0)). Regular application data will flow through the Avalon-MM Rx Maste port.


From the user guide specified above:


"After servicing the interrupt, software must clear the appropriate serviced interrupt status bit and ensure

that no other interrupts are pending. For interrupts caused by Avalon-MM to PCI Express Interrupt

Status Register mailbox writes, the status bits should be cleared in the Avalon-MM to PCI Express

Interrupt Status Register. For interrupts due to the incoming interrupt signals on the Avalon-MM

interface, the interrupt status should be cleared in the Avalon-MM component that sourced the interrupt.

This sequence prevents interrupt requests from being lost during interrupt servicing."



My question:

How can the application side know when the root port side has taken care of the interrupt? When to deassert the RXirq_irq(15:0) signal without the risk that the interrupt request inside the IP getting lost?


RXirq_irq(15:0) is edge sensitive and a rising edge trigger an MSI interrupt. Does that mean the the RXirq_irq signal only need to be asserted for 62,5 MHz pulse?


Kind regards







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1 Reply

Hi Sir,


I believe the interrupt that you talking here is the MSI/MSIX?


For PCIe, MSI is transmitted as posted memory write, so no completer is needed. Thus, application just assume the RP side already taken care the interrupt unless RP return NAK.


For second question regarding the pulse width, I believe your concern is since there is to acknowledgment from RP about the interrupt, then how long you should hold it. Answer is yes, 62.5MHz pulse is ok as long as there is rising edge.

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