PCI Express IP Core in 64-bit addressing mode

FPGA Intellectual Property

PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP

PCI Express IP Core in 64-bit addressing mode

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All the functional models for PCI Express IP Core demos work in the mode of addressing 32 bits (the packet header is 12 bytes or 3 words). How do I get a functional model for 64-bit addressing mode in which the header is 16 bytes (4 words)?

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