PCI Express - chaining DMA - newbie Q

[Altera_Forum]

hello, 

 i'm stuck (rather newbie) and would like to ask if i'm taking the right approach.   i used the pci express compiler user guide 8.0 using the megawizard to create a pci express soft core.   it is for a (custom) cyclone ii device/board connected to a nxp1011a pcie phy.   the megawizard also generates the "chaining dma example design" described in chapter 7 of the compiler user guide. i have used 4 kb bar2:3 regions.   i have generated a symbol for "pcie_example_chaining_top.vhd" in the \prj\pcie_examples\chaining_dma. i then put this on my toplevel.bdf and connect it with the pins to the phy.   when i compile/synthesize this, i notice that the design does occupies ~1500 cells, ~570 registers, but no memory.   how can this be? doesn't the design need 2x 4kb memory for the bars?   maybe i missed something? also, which files would i need to add to my project?    Thanks for any hints,   Leon.

[Altera_Forum]

Not sure what is wrong. PCIE_example_chaining_top.vhd should be the top level file for the design. I have never tried making and using a .bdf file before.  

 What happens if you open and compile the PCIE_example_chaining_top.qpf project file? That should give you the complete design. You should be able to just make the pin assignments for your board in this project.

[Altera_Forum]

Thank you. 

 Opening the example project showed that it included pcie.vhd (I named the soft core "pcie") but also pcie_core.vhd into the project.  That one was missing from my project. It drags in the .ipa file, which presumably makes sure the IP gets dragged in?  I'll redo this from scratch and write it down as a short reference.  More questions down the road. :-)

[Altera_Forum]

Just a quick reply, I have written a driver and submitted it to the Linux kernel tree. It was accepted and now lives in the staging area until cleaned up.

[Altera_Forum]

Hello, 

 Thanks a lot to *likewise* for writing and publishing the linux driver. It gave me a very good point to start. And actually it worked great for me. I am using an Arria GX Development Kit. Now i have to port the driver to another realtime operating system. Unfortunately i don't get MSI (Message Signaled Interrupts) to run with that other operating system. What would i have to change on the driver to use legacy interrupts instead? Is it possible at all, or do i have to change the FPGA image?  I assume i have to write a different value to w0... but what exactly?   --- Quote Start ---  ape->table_virt->desc[n].w0 |= cpu_to_le32(1UL << 16)/*local MSI*/;  --- Quote End ---    Unfortunately my own knowlede about FPGA is very limited. Where can i get that information? I currently just use the standard image that came installed with the Development Kit.  Thanks a lot!

[Altera_Forum]

Thank you for reporting your success here, it helps me get the driver accepted in mainstream Linux. 

 There are issues with the legacy-interrupt mechanism in the 8.x series of the chaining DMA example.  I may have some emails and notes to report back here, but maybe others can help, as I did not test nor use non-MSI.  The driver should work with legacy interrupts once the FPGA logic works correctly.

[Altera_Forum]

Hey, likewise, I'll report success here, too. I've successfully loaded your driver using an AGX board, but only for design examples compiled in 7.2 and now 9.0. Something is wrong with the 8.x examples, and I can't even get my computer to recognize the board when it is running them. I've noticed that Altera reintroduced the "preliminary design" warning to 9.0 that also popped up in 7.2, and I wonder if they had to revert, or what it is they're doing. ???

[Altera_Forum]

TO_BE_DONE

[Altera_Forum]

Hi everyone. 

 I second vineetchadha; I'm getting the same error. Any idea what might be causing it?  I'm using Quartus 11.1 and a Arria GX II.  Best regards to all, Pedro

[Altera_Forum]

Hi,  

 I too have the same error. What is causing it?  My system is similar to Pedro.  Thanks.