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Altera_Forum
Honored Contributor I
1,270 Views

PCIE link -up status

Hi , I am migrating an old design i had using a soft PCIE core to cyclone 4's hard IP. I had a 'link-up' status signal which I used to drive an LED whenever the link became active. Is there an equivalent in the PCIE hard IP implementation in QSYS. In the reference designs it seems the test_out signals played a similar role but not sure exactly how it works. thanks

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Altera_Forum
Honored Contributor I
160 Views

The link is consider up when the 10G MAC successfully transmit or receive idle to/from the link partner. Use the 10g MAC "link_fault_status_xgmii_rx" output.  

 

1) link_idle = 2b'00 <- after powerup, this show link idle because the system is still in reset stage. 

 

2) link_training = 2b'01 <- after transceiver reset sequence is complete, the link is still not stable and trying to transmit the idle here. 

 

3) link_up = 2'b00 <- the link is stable and successfully transmit/receive idle, the mac will show link up.
Altera_Forum
Honored Contributor I
160 Views

pcie_hard_ip_0_fixedclk_clk : in std_logic := '0'; -- pcie_hard_ip_0_fixedclk.clk 

pcie_hard_ip_0_pipe_ext_pipe_mode : in std_logic := '0'; -- pcie_hard_ip_0_pipe_ext.pipe_mode 

pcie_hard_ip_0_pipe_ext_phystatus_ext : in std_logic := '0'; -- .phystatus_ext 

pcie_hard_ip_0_pipe_ext_pll_powerdown : in std_logic := '0'; -- .pll_powerdown 

pcie_hard_ip_0_pipe_ext_gxb_powerdown : in std_logic := '0'; -- .gxb_powerdown 

pcie_hard_ip_0_pipe_ext_rate_ext : out std_logic; -- .rate_ext 

pcie_hard_ip_0_pipe_ext_powerdown_ext : out std_logic_vector(1 downto 0); -- .powerdown_ext 

pcie_hard_ip_0_pipe_ext_txdetectrx_ext : out std_logic; -- .txdetectrx_ext 

pcie_hard_ip_0_pipe_ext_rxelecidle0_ext : in std_logic := '0'; -- .rxelecidle0_ext 

pcie_hard_ip_0_pipe_ext_rxdata0_ext : in std_logic_vector(7 downto 0) := (others => '0'); -- .rxdata0_ext 

pcie_hard_ip_0_pipe_ext_rxstatus0_ext : in std_logic_vector(2 downto 0) := (others => '0'); -- .rxstatus0_ext 

pcie_hard_ip_0_pipe_ext_rxvalid0_ext : in std_logic := '0'; -- .rxvalid0_ext 

pcie_hard_ip_0_pipe_ext_rxdatak0_ext : in std_logic := '0'; -- .rxdatak0_ext 

pcie_hard_ip_0_pipe_ext_txdata0_ext : out std_logic_vector(7 downto 0); -- .txdata0_ext 

pcie_hard_ip_0_pipe_ext_txdatak0_ext : out std_logic; -- .txdatak0_ext 

pcie_hard_ip_0_pipe_ext_rxpolarity0_ext : out std_logic; -- .rxpolarity0_ext 

pcie_hard_ip_0_pipe_ext_txcompl0_ext : out std_logic; -- .txcompl0_ext 

pcie_hard_ip_0_pipe_ext_txelecidle0_ext : out std_logic; -- .txelecidle0_ext 

pcie_hard_ip_0_cal_blk_clk_clk : in std_logic := '0'; -- pcie_hard_ip_0_cal_blk_clk.clk 

pcie_hard_ip_0_reconfig_togxb_data : in std_logic_vector(3 downto 0) := (others => '0'); -- pcie_hard_ip_0_reconfig_togxb.data 

pcie_hard_ip_0_reconfig_busy_busy_altgxb_reconfig : in std_logic := '0'; -- pcie_hard_ip_0_reconfig_busy.busy_altgxb_reconfig 

pcie_hard_ip_0_pcie_rstn_export : in std_logic := '0'; -- pcie_hard_ip_0_pcie_rstn.export 

pcie_hard_ip_0_test_out_test_out : out std_logic_vector(63 downto 0); -- pcie_hard_ip_0_test_out.test_out 

pcie_hard_ip_0_rx_in_rx_datain_0 : in std_logic := '0'; -- pcie_hard_ip_0_rx_in.rx_datain_0 

pcie_hard_ip_0_reconfig_fromgxb_0_data : out std_logic_vector(4 downto 0); -- pcie_hard_ip_0_reconfig_fromgxb_0.data 

pcie_hard_ip_0_reconfig_gxbclk_clk : in std_logic := '0'; -- pcie_hard_ip_0_reconfig_gxbclk.clk 

pcie_hard_ip_0_tx_out_tx_dataout_0 : out std_logic; -- pcie_hard_ip_0_tx_out.tx_dataout_0 

pcie_hard_ip_0_clocks_sim_clk250_export : out std_logic; -- pcie_hard_ip_0_clocks_sim.clk250_export 

pcie_hard_ip_0_clocks_sim_clk500_export : out std_logic; -- .clk500_export 

pcie_hard_ip_0_clocks_sim_clk125_export : out std_logic; -- .clk125_export 

pcie_hard_ip_0_test_in_test_in : in std_logic_vector(39 downto 0) := (others => '0'); -- pcie_hard_ip_0_test_in.test_in 

pcie_hard_ip_0_refclk_export : in std_logic := '0' --  

 

 

this is the top level for the system i generated in QSYS (+plus some other signals from my custom components)  

 

none of these is the "k_fault_status_xgmii_rx" do i need to change some settings in order for this signal to come up? My system consist of a 1 lane PCIE hard IP, DMA and a custom memory-like module.
Altera_Forum
Honored Contributor I
160 Views

Sorry about the 10g link up answer - wrong post.  

I do have an PCIe Qsys block in our Stratix IV device. From Qsys, I instantiated an "IP_Compiler for PCI Express" (altera_pcie_hard_ip) component. This component provides a "pcie_rstn" output. We use this output as a link up status. We started with Beta Qsys software and now are using 11.0sp1. I mention this because your PICe ports are slightly different than what I have. I am not sure if it is because we started from Beta software or because you using a different Qsys component
Altera_Forum
Honored Contributor I
160 Views

i'll try this. Thanks for the response.

Altera_Forum
Honored Contributor I
160 Views

"pcie_rstn" is the PCIe edge connector reset line, so you can detect when you are hot-plugged into a host or the bus is reset. Not much point in showing this. 

 

For link state, read the datasheet, and you will find a couple of bits in pcie_hard_ip_0_test_out_test_out show what you are looking for. LTSSM states are useful to decode if you have enough LEDs - PCIe in L0 state usually is good enough for single bit display.