FPGA Intellectual Property

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FPGA Intellectual Property

Discussions

Interfacing SGDMA with custom component

DCFIFO simultaneous read and write problem

CIC compensation filers (FIR)

Using DSP block for CRC calculation

ASI Megafunction and the Data Valid

AvalonST FIFO

ALTMEMPHY port replication/DDIO_OUT WYSIWYG invalid splitter fan out

DDR3 SDRAM Controller - issues caused by enabling the Efficiency Monitor !!!

TSE in 100MBit

How to get license for Altera DSP Builder

HPCII for DDR2 problem: Clock and initialization always low

help:DDR2 can't init done

Copy Video Stream Several Times

Using Stratix V Transceiver native PHY core in the place of Arriai V PHY core

PCIe Cyclone V CRA Register

Featured Content

Tone Mapping Operator IP Malfunctioning

dynamic configuration issue of fpll from arria 10

AGILEX 5E : GTS AXI IP PCI Express : What is the mapping of the PCIe Header on _tuser_hdr[255:0]

Re: ALTPLL dynamic phase shift: c0/c1 shift in opposite directions; c2 does not shift (Stratix IV)

Re: ALTPLL dynamic phase shift: c0/c1 shift in opposite directions; c2 does not shift (Stratix IV)