12-06-2012 08:54 AM
HiI'm doing a qsys design which is composed of a sdi rx, a clocked video input, a deinterlacer, an interlacer, a clocked video output, and a sdi tx. This design simply receives an interlaced sdi video and outputs the interlaced sdi video in the same video standard as the input. I know the deinterlacer and interlacer may be redundant for now. But my next step will add a scaler between the deinterlacer and the scaler requires progressive video. In my current design, progressive video input such as 720p60 works fine but interlaced video inputs cause a flickered display. I also find the underflow occurs in the clocked video output. I've tried to use double buffer in deinterlacer (algorithm uses Bob duplication) and turned on "accept sync. output" in clocked video input and clocked video output. But none of this trials work. Could anyone please provide me any idea to solve this problem? Thanks.
12-06-2012 02:23 PM
Hi SocratesThank you for the reply. You really help me a lot on my SDI project. I'm wondering how I can check whether the sdi reception clock is inaccurate. Because I generate the sdi input video by the rtl code provided in Altera SDI example, I doubt that the timing of the sdi input may not be very accurate. This generated sdi input video can be received by SDI receiver. I can see frame locked by checking rx_status. But I'm not sure about if the input video is very accurate. About the Genlock, I'm confused. Is Genlock a technique which can be done in SDI IP or an additional chip on PCB? I may need more time to study Genlock. Thanks again.
12-06-2012 02:54 PM
You need additional chip, which recovers SDI clock from SDI input. That chip will provide clock to Your FPGA. And yes, You need to read more about genlock.