PCIe HIP in SOPC simulation questions

[Altera_Forum]

I'm going through the training course PCI Express Hard IP Quick Start Guide with SOPC Builder to get a feel for the PCIe IP. I'm simulating the testbench that the PCI Express Compiler creates but I'm frustrated with how this flow is working. There are a couple of tcl files created to make the simulation "easy". The first one is setup_sim.do that sets up some aliases like 'c' to compile the whole design and 'w' to populate the wave window.  

 1. When I run 'c' the design does compile but it compiles all sorts of things into the work library that I don't think need to be there. There are groups of arriaii*, cycloneiv*, hardcopyiv*, stratixiigx*, and stratixiv* all compiled into my work library. It takes forever to finish. Why aren't the Altera libraries just referenced instead of being compiled into my work directory?   2. When I run 'w' none of the signals are visible. I have to go back and explicitly recompile the testbench without optimization with 'vsim -novopt work.test_bench'. After waiting for that to finish (see# 1) I can rum 'w' and see all my signals.    I would think a demo would work easily. Is there something I'm doing wrong?   Thanks

[Altera_Forum]

Hi, 

 Sorry I can't answer your questions (yet). I assume you've compiled this already in ModelSim. Did you get any errors about unconnected ports? Here's what I get when I run runtb.do in ModelSim for QII 9.1:    --- Quote Start ---   Loading work.altpcierd_write_dma_requester_128# Loading work.altpcierd_read_dma_requester_128# Loading work.altpcierd_cdma_ast_tx_128# Loading work.altpcierd_cdma_ast_rx_128# ** Warning: (vsim-3017) ./pci_test_chaining_testbench.v(655): [TFMPC] - Too few port connections. Expected 116, found 114.# Region: /pci_test_chaining_testbench/ep# ** Warning: (vsim-3722) ./pci_test_chaining_testbench.v(655): [TFMPC] - Missing connection for port 'gen2_speed'.# ** Warning: (vsim-3722) ./pci_test_chaining_testbench.v(655): [TFMPC] - Missing connection for port 'tx_st_err0'.# ** Warning: (vsim-3017) ../pci_test_example_chaining_pipen1b.v(799): [TFMPC] - Too few port connections. Expected 186, found 175.# Region: /pci_test_chaining_testbench/ep/epmap# ** Warning: (vsim-3722) ../pci_test_example_chaining_pipen1b.v(799): [TFMPC] - Missing connection for port 'derr_cor_ext_rcv0'.# ** Warning: (vsim-3722) ../pci_test_example_chaining_pipen1b.v(799): [TFMPC] - Missing connection for port 'derr_cor_ext_rpl'.# ** Warning: (vsim-3722) ../pci_test_example_chaining_pipen1b.v(799): [TFMPC] - Missing connection for port 'derr_rpl'.# ** Warning: (vsim-3722) ../pci_test_example_chaining_pipen1b.v(799): [TFMPC] - Missing connection for port 'ko_cpl_spc_vc0'.# ** Warning: (vsim-3722) ../pci_test_example_chaining_pipen1b.v(799): [TFMPC] - Missing connection for port 'npd_alloc_1cred_vc0'.# ** Warning: (vsim-3722) ../pci_test_example_chaining_pipen1b.v(799): [TFMPC] - Missing connection for port 'npd_cred_vio_vc0'.# ** Warning: (vsim-3722) ../pci_test_example_chaining_pipen1b.v(799): [TFMPC] - Missing connection for port 'nph_alloc_1cred_vc0'.# ** Warning: (vsim-3722) ../pci_test_example_chaining_pipen1b.v(799): [TFMPC] - Missing connection for port 'nph_cred_vio_vc0'.# ** Warning: (vsim-3722) ../pci_test_example_chaining_pipen1b.v(799): [TFMPC] - Missing connection for port 'r2c_err0'.# ** Warning: (vsim-3722) ../pci_test_example_chaining_pipen1b.v(799): [TFMPC] - Missing connection for port 'reset_status'.# ** Warning: (vsim-3722) ../pci_test_example_chaining_pipen1b.v(799): [TFMPC] - Missing connection for port 'suc_spd_neg'.# ** Warning: (vsim-3017) ../../../pci_test.v(978): [TFMPC] - Too few port connections. Expected 39, found 36.# Region: /pci_test_chaining_testbench/ep/epmap/serdes# ** Warning: (vsim-3722) ../../../pci_test.v(978): [TFMPC] - Missing connection for port 'coreclkout'.# ** Warning: (vsim-3722) ../../../pci_test.v(978): [TFMPC] - Missing connection for port 'rx_patterndetect'.# ** Warning: (vsim-3722) ../../../pci_test.v(978): [TFMPC] - Missing connection for port 'rx_syncstatus'.# ** Warning: (vsim-3017) ../../../pci_test.v(1214): [TFMPC] - Too few port connections. Expected 243, found 231.# Region: /pci_test_chaining_testbench/ep/epmap/wrapper# ** Warning: (vsim-3722) ../../../pci_test.v(1214): [TFMPC] - Missing connection for port 'avs_pcie_reconfig_readdata'.# ** Warning: (vsim-3722) ../../../pci_test.v(1214): [TFMPC] - Missing connection for port 'avs_pcie_reconfig_readdatavalid'.# ** Warning: (vsim-3722) ../../../pci_test.v(1214): [TFMPC] - Missing connection for port 'avs_pcie_reconfig_waitrequest'.# ** Warning: (vsim-3722) ../../../pci_test.v(1214): [TFMPC] - Missing connection for port 'dprioreset'.# ** Warning: (vsim-3722) ../../../pci_test.v(1214): [TFMPC] - Missing connection for port 'ev_128ns'.# ** Warning: (vsim-3722) ../../../pci_test.v(1214): [TFMPC] - Missing connection for port 'ev_1us'.# ** Warning: (vsim-3722) ../../../pci_test.v(1214): [TFMPC] - Missing connection for port 'int_status'.# ** Warning: (vsim-3722) ../../../pci_test.v(1214): [TFMPC] - Missing connection for port 'serr_out'.# ** Warning: (vsim-3722) ../../../pci_test.v(1214): [TFMPC] - Missing connection for port 'swdn_wake'.# ** Warning: (vsim-3722) ../../../pci_test.v(1214): [TFMPC] - Missing connection for port 'swup_hotrst'.# ** Warning: (vsim-3722) ../../../pci_test.v(1214): [TFMPC] - Missing connection for port 'use_pcie_reconfig'.# ** Warning: (vsim-3722) ../../../pci_test.v(1214): [TFMPC] - Missing connection for port 'wake_oen'.# ** Error: (vsim-3389) ../../../pci_test_core.vo(2483): Port 'extraclkout' not found in the connected module (83rd connection).# Region: /pci_test_chaining_testbench/ep/epmap/wrapper/n010ii# ** Error: (vsim-3389) ../../../pci_test_core.vo(2483): Port 'r2cerr0ext' not found in the connected module (114th connection).# Region: /pci_test_chaining_testbench/ep/epmap/wrapper/n010ii# ** Error: (vsim-3389) ../../../pci_test_core.vo(2483): Port 'successspeednegoint' not found in the connected module (159th connection).# Region: /pci_test_chaining_testbench/ep/epmap/wrapper/n010ii# ** Fatal: (vsim-3365) ../../../pci_test_core.vo(2483): Too many port connections. Expected 219, found 222.# Time: 0 ps Iteration: 0 Instance: /pci_test_chaining_testbench/ep/epmap/wrapper/n010ii File: C:/tools/altera/91/modelsim_ase/win32aloem/../altera/verilog/src/stratixiv_pcie_hip_atoms.v# FATAL ERROR while loading design# Error loading design  --- Quote End ---  

[Altera_Forum]

It looks like you are running the non-SOPC version. I did simulate that one a while ago. I don't remember there being any problems. Right now I 'm using the SOPC version and trying to tie the PCIe to a NIOS II.

[Altera_Forum]

All I did was instantiate a PCIe component and ran the TB with no modification. It's weird that there should be any errors with this. 

 At least with the Avalon-ST variant I'm compiling it's only pulling in the stratixiv* libs (my target FPGA).  Have you tried commenting out the vlib/vmap/vlog statements associated with the other FPGA families it's pulling in, in the .do file? In my .do file, these statements are conditional on stratixiv_hssi_atoms.v existing in the build.  Peter

[Altera_Forum]

I too am having trouble with the PCIe demo. Note that the Web Edition of Quartus II does not include support for Stratus IV devices, although the Qsys demo seems to require some Stratus IV files: 

 “triple double-you dot altera.com/literature/po/ss_quartussevswe.pdf”  I will try to extract these files from the Standard Edition and see if I can get the demo to build.

[Altera_Forum]

The attached zip archive contains the missing "stratixiv" files that are needed to build the "PCI Express Hard IP Design with Qsys" exercise. These files should be placed in the following directory: 

 "C:\altera\11.0sp1\quartus\eda\sim_lib"   This step is only necessary if you are using the Web Edition of Quartus 11.0sp1. The Subscription Edition already contains these files.

[Altera_Forum]

All I did was instantiate a PCIe :) http://www.qhd95598.com.cn/us.jpg