PCIe Hard IP Cyclone 10 GX is not Detect in PC

[JKoty]

Hi,

we own DK-DEV-10CX220-A Cyclone 10GX DevKit. we are using Quartus Prime Version 18.1.0 Build 222 09/21/2018 SJ Pro Edition. We are implementing Hard PCIe IP (18.1, altera_pcie_a10_hip, Intel Arria 10/Cyclone 10 Hard IP for PCI Express - Gen1:x4, Interface: 64bit, 125MHz) into dev kit. But after generating .sof file / .jic file and upload into FGPA, PC is not able to detect PCIe device (PC -optiflex 9020 with Ubuntu 20.04 clean installation ) we tried soft reset PC also Bios enumeration command after boot. I would like to ask for help to find solution for this issue.

Best regards

Jan

[Rahul_S_Intel1]

Hi Jan,

The above problem is occured due to , you did not configure the PCIe IP correctly . May be the PCIe is in reset state.

Can you please provide the LTSSM state signal tap for my reference.

[JKoty]

Hi,

I was able to scan status of basic signals some times after start. I am not sure how to trigger initial sequence for PCIe (If it is necessary for you) because Signaltap load image/ power cycle delay and so on... but for now it is looks like PCIe is stuck in state 03h - polling.compliance state

This design is reference design :

https://www.intel.com/content/www/us/en/programmable/documentation/ecx1522703736467.html, https://fpgacloud.intel.com/devstore/platform/2183/

So pins and others project depend settings should be done correctly, but I can share with you some post build logs.

Quartus only ask me for update IP core:

But I do not thing that is really important for detecting PCIe in PC - what is my goal for now.

Best Regards

Jan

[Rahul_S_Intel1]

Hi Jan ,

The LTSSM state is showing an incorrect and is expecting 0FH , can you compile the design in the respected version .

[JKoty]

Hi,

we find solution/ workaround. We tried few PC and some worked correctly (in AS mode and without external PS) but some of then needed external PS, we used delivered power supply. After that it is works.

Thank you

Jan