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Hi All,
System configure:
OS: Win10
QII: 19.3
FPGA: 1SG280HH1F55I1VG
DOC: UG20032, UG20053, UG20170 , AN811
Question:
I follow the "Create the design example" section of those UG but fail to create a design example. It report error when I press "Generate Example Design" in Platform Designer. Please provide some advice for fix the issue.
Information attached:
Qsys file
Copy of error message
Log file
Thx
Albert
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Hi,
In order to better assist you, could you please share with us the PCIe *.ip file, so that I can get the exact same setting as yours and try to generate the example design. Thanks.
Regards -SK
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Dear SK,
As attached.
Thx.
Albert,
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