PCIe RAS DES Features Enabling

[LAH20]

Hello ,

I would like to know how to enable the Synopsys RAS DES Features of the R-tile Hard IP for the Agilex FPGA and also how to access these registers. I have gone through the ug20316.pdf document and could not find any information regarding this. 

Thanks!

Any insight would be appreciated.

[KhaiChein_Y_Intel]

Hi,

This information is not available as R-tile document is not yet officially released.

Thanks

Best regards,

KhaiY

[LAH20]

Hello ,

Do you know when this document would be available?

Thanks!

[KhaiChein_Y_Intel]

Hi,

I am afraid that I cannot share the product release timeline in the public. I am sorry for the inconvenience caused.

Thanks

Best regards,

KhaiY

[KhaiChein_Y_Intel]

Hi,

Since we have communicated internally and there is no other questions, this thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you

Best regards,

KhaiY