FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6356 Discussions

PCIe RAS DES Features Enabling

LAH20
Employee
633 Views

Hello ,

I would like to know how to enable the Synopsys RAS DES Features of the R-tile Hard IP for the Agilex FPGA and also how to access these registers. I have gone through the ug20316.pdf document and could not find any information regarding this. 

Thanks!

Any insight would be appreciated.

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4 Replies
KhaiChein_Y_Intel
618 Views

Hi,


This information is not available as R-tile document is not yet officially released.


Thanks

Best regards,

KhaiY


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LAH20
Employee
605 Views

Hello ,

 

Do you know when this document would be available?

 

Thanks!

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KhaiChein_Y_Intel
587 Views

Hi,


I am afraid that I cannot share the product release timeline in the public. I am sorry for the inconvenience caused.


Thanks

Best regards,

KhaiY


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KhaiChein_Y_Intel
578 Views

Hi,


Since we have communicated internally and there is no other questions, this thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you


Best regards,

KhaiY


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