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PCIe SR-IOV Arria 10 Configuration Space

agula
New Contributor I
208 Views

Hi All,

 

Is the configuration space handled completely by the IP, or does the memory for the configuration space exist in your application logic memory. For example, is it in the user-space bar logic of your physical or virtual function ? If I am trying to generate MSI-X interrupts, do I need to manually write to the MSI-X capability struct at address 10h of the configuration space or is this handled completely by  the PCIe driver API calls.

Thank you

 

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4 Replies
BoonT_Intel
Moderator
194 Views

Hello Sir,

 

For MSI-X, you will need to configure the parameters in the IP GUI as below:

IP Settings -> Interrupt capabilities -> PF0 (VF) MSI-X

BoonT_Intel_0-1608023095103.png

 

And this parameters is map to the Figure 46 “MSI-X Capability Registers” as describe in the UG- https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_pcie_sriov.pdf#pa...

So, from the host (driver), you will need read these MSI-X capabilities register to check the table and PBA offset. 

 

agula
New Contributor I
185 Views

Hi !

 

Thanks for your reply. Could you please try to elaborate more ? I am not sure , I get the complete picture. Based on what I read, the table size is equivalent to how many vectors can be generated. If you set the VF msi-x table size to 2. Does this mean you have two distinct interrupts that can be generated ?  Does this also mean that every other VF also has this msi-x table of size 2  as well ?

 

I also need more clarification on where the msi-x table and pba table actually reside. For example, if I set BIR to be 0 for VFs. Where does this table actually reside? Is it in the user-application on-chip memory of the VF bar0  at address offset 0 ? Then to generate an interrupt for VF 1 go to that memory location read the addresses and set the request and set the PBA to the appropriate value ?

 

Based on the documentation provided in the user guide. It seems to me that the user-application logic needs to know, where the MSI-X table is to read the address and data for a specific interrupt to trigger. 

BoonT_Intel
Moderator
161 Views

Hi Sir,

Let me try to answer one by one:


If you set the VF msi-x table size to 2. Does this mean you have two distinct interrupts that can be generated? -> Yes

Does this also mean that every other VF also has this msi-x table of size 2 as well? -> Yes


You can see the table is actually assigned to a BAR that you set in the GUI. And you have to define the table by yourself. The table that mentions here is in Figure 32. Format of MSI-X Table.


I also need more clarification on where the msi-x table and pba table actually reside. For example, if I set BIR to be 0 for VFs. Where does this table actually reside? Is it in the user-application on-chip memory of the VF bar0 at address offset 0? Then to generate an interrupt for VF 1 go to that memory location read the addresses and set the request and set the PBA to the appropriate value?

è If I understand your questions correctly, then the answer is yes for all. It is depending on what component you connect the MSI-X BAR. Most of the user connects it to an on-chip memory that contains the MSI-X table. For details, you may see Figure 31. MSI-X Interrupt Components. Items 1-5.


BoonT_Intel
Moderator
147 Views

We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


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