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PCIe SRIOV Avalon Stream Gen 3 automatically generate locked read request

PPham3
Beginner
1,423 Views

Hi all,

I have a problem with PCIe SRIOV avalon stream. I used SRIOV example design but tried to take the tx stream and rx stream out of the APP function. When I get those signal to signaltap. I noticed that some unwanted packet just streaming down through rx stream though the sw did not write or read anything. The packet format look like a locked read request( 8 lsb bits are 0x01h). Is this issue happens to anyone? How to get it work? Thanks.

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1 Solution
SengKok_L_Intel
Moderator
383 Views

You need APPS in order to make your design fully function. Without the APPS, the Host should still detect end points, and I don't aware any specify signal need to be connected.

 

Regards -SK  ​

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11 Replies
SengKok_L_Intel
Moderator
383 Views

Hi,

 

The lock request is performed between a Root Port and the Legacy Endpoint. Perhaps, you may provide more information like what device you are using, or what application you are running and observe this behavior. ​Are there a concern of memory read or write request?

PPham3
Beginner
383 Views

I made a mistake. It was not a read req message, it's type just appears to be broadcast message from root complex. Just dont know why this message is automatically sent down.

By the way, when I use the hard ip only, pcie is not detected through lspci from linux. Everything works when using example design, anyone faces this problem?

Thanks​

SengKok_L_Intel
Moderator
383 Views

I assume that you are removed the APPS from the design but left the DUT alone. If this is the case, the OS should be still able to detect the PCIe end point.

 

Regards -SK Lim​

PPham3
Beginner
383 Views

You were right. I removed the apps and kept dut. PCIE was not detected.

SengKok_L_Intel
Moderator
383 Views

You may need to check if the LTSSM still achieve L0 after rebooting the PC, if yes, the end point should be there.

 

Regards -SK Lim

PPham3
Beginner
383 Views

Hi SK Lim,

I did not check LTSSM signal. Was that signal meaningful for simulation only?

Still can not bring PCIe up without the APPS part? could you please give me a hint about connection? what the APPS really does to make this design work?

Thanks.

SengKok_L_Intel
Moderator
383 Views

Removing the APPS, by right the Host should can still detect the end point. Check the LTSSM is to ensure the Link is still up. The host is not able to detect end point IF the LTSSM can't achieve L0. The APPS is required to decode and process the Header for Memory Read/Memory write TLP.

 

Regards -SK​

SengKok_L_Intel
Moderator
383 Views

​Anyhow, you need the APPS to process the Memory read/Memory write and create the completion TLP. You can use the APPS in the example design to modify or update based on your design requirement. Or you can create your own APPS. It does not make sense to left the Avalon ST unconnected.

 

Regards -SK Lim

PPham3
Beginner
383 Views

the reason why I do not want to use the APPS is to generate 4 PFs. at this point, the APPS is not supported (maximum 2 PFs for the APPS).

Still many thing to work since when I generate 2 PFs via example design, each PF has 8 VFs. The linux lspci can detect 1 PF and full 8 VFs, still one more PF missing. Is there any special signal that must be connected to make this design work

?

Thanks so much, SK Lim.

SengKok_L_Intel
Moderator
384 Views

You need APPS in order to make your design fully function. Without the APPS, the Host should still detect end points, and I don't aware any specify signal need to be connected.

 

Regards -SK  ​

PPham3
Beginner
383 Views

Okay, thank you. It seems that I need to make it out on my own.

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