Good morning,I have a misfunction concerning (I think) a PCIe module embedded in a Cyclone V FPGA. Please, find below my setting as well as the observations I made. - My setting : - A laboratory power supply powers the host computer, - The host computer running GNU/Linux. - My mini PCIe card is connected to the mini PCIe connector inside the host computer, - The Cyclone V FPGA is located on this mini PCIe card. - What I observed and I consider OK: - When I first switch-on the laboratory power supply, the mother board is powered and the mini PCIe card also, - Thus, the FPGA is programmed. For information, the programmation time is less than 100ms (checked with an oscilloscope), - When I push-down the power button of the host computer, it starts and it detects the Mini PCIe card. - What I observed and I consider not OK and I have difficulties to find out why: - When a warm reset is done (push-down on reset button), after a random number of time (around 2 -> 20), the mini PCIe card is not detected anymore. It will be detected again after a cold reset (cut-off the lab. power supply and re power-up the host, etc...). For information : after the reset, the FPGA is still configured as the motherboard and thus the mini PCIe card are staying powered. - When a shutdown is done (systemctl poweroff --force --force), the same behavior is observed. I checked the PCIe configuration (under QSys) as well as the connection to the npor and perst signals. I have seen nothing wrong. I checked the user guide from Altera, as well as its forum but unfortunately I couldn't find relevant informations. Also, I'm new in this PCIe topic, so maybe I missed something obvious. Also : - my design uses a PLL (Altera_PLL) to clock my cpu plus some others modules. - The PCie parts (Avalon-MM Cyclone V Hard IP for PCI Express, Altera PCIe Reconfig Driver, Transceiver Rconfiguration Controller) are depending on their own clock : pin_L4, the dedicated PCIe clock input. I discovered that if I connect the PERST signal to the reset (rst) input of the PLL (Altera_PLL, used to clock my cpu plus some others modules) then this "PCIe detection card" issue is gone. I consider it gone as I did around 60 times a warm reset and the PCIe was still detected. Before I did that, the "rst" input was grounded (not sure if it is the right thing to do by the way). Basically, I wanted to check the effect on the functionality when the host PC assert the PERST signal after a reset. As the reset input of the PLL is active High, I use an inverter. In that way, the PLL is reset when the PERST signal is asserted. That "work around" seems to solve this issue but I am not sure if it is the right way to do and if it was the origin of this issue. Do you have an idea or any suggestion where to investigate please? Thank you for your help.