FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP

QSYS FFT 16.0 issue

Altera_Forum
Honored Contributor II
1,010 Views

Hi, 

 

I’m trying to generate FFT 16.0 Core with QSYS. With the setting shown in the attached file the generated code can be synthesized. If I change Data Input Width and Twiddle Width to 32 Bit the .hex files will be generated wrong. 

 

fft_core_fft_ii_0_1n64sin.hex 

:03000000000000fd 

:030001000c8bd35c36 

:0300020018f8b83cf7 

 

As you can see fft_core_fft_ii_0_1n64sin.hex the length of the first doesn't match to the length of other lines. 

 

Output from Quartus: Error (113029): Data size does not match the number of bytes at line 2 in Hexadecimal (Intel-Format) File "fft_core_fft_ii_0_1n64sin.hex" 

 

How to fix this problem? 

 

Best regards  

Samuel
0 Kudos
1 Reply
Altera_Forum
Honored Contributor II
295 Views

The problem is still open. I attached the qsys files, the bug should easily be reproduced. 

 

Thank you for your help
0 Kudos
Reply