I wonder if you guys could have a quick look at my configuration for the PCIe Hard IP for Stratix V. I am looking to combine BAR4 and BAR5 on the PCIe IP to provide a 64-bit address to an external component. I started out with a PCIe module using BAR0 – BAR3 that we have been using and that seems to work fine.
Now for the BAR4 updates:
In Platform Designer, I set BAR4 to 64-bit prefetchable memory which combines BAR4 and BAR5 to provide a 64-bit address space. Under “Avalon-MM System Settings” I changed the Avalon address width to 64-bit from 32. Everything else stayed the same. I then added a Pipeline Bridge to bring out BAR4 from the Platform Designer system. The data width of the bridge is 64-bits and the address width is 34-bits (I only needed 34 of the 64 address bits). See images below for IP configuration settings for Hard IP and bridge. Platform designer doesn’t give me any errors and the project compiles just fine.
However, I ran into a problem this weekend when I loaded the image into flash on our development board. When I rebooted the PC so the image would take effect, the PC would not boot. It just seems to reset constantly. I don’t get any output on the monitor, no BIOS messages, no Windows splash screen, nothing.
I noticed that I forgot to update the “address width of accessible PCIe address space” setting at the bottom of the configuration screen. It was set to 32-bits. I have updated this from 32 to 34-bits. I reloaded the new image this morning and the PC crashed again.
Without the addition of my BAR4 updates, the PCI IP seems to work fine. Have you got any insights as to why the updated PCI module would cause the PC not to boot? Is there a configuration setting that I got wrong?
Thanks for any help you can provide.