PCIe hard IP and SerDes Transceiver Configuration in Cyclone V GX with 6 transceivers

[MaHa1]

Dear Intel Community and Intel Employees,

I need to place one PCIe Gen1 x1 hard IP block and 4 SerDes Transceiver Channels of an third party IP of an switch into a Cyclone V GX with 6 transceivers (5CGXFC7C6U19I7).

triplet	transceiver	usage
0	0	PCIe hard IP
0	1	unused / CMU of PCIe
0	2	SerDes HSR ring 1 : Port 0
1	3	SerDes HSR ring 1 : Port 1
1	4	SerDes HSR ring 2 : Port 0
1	5	SerDes HSR ring 2 : Port 1

but I get the error:

Error (11687): Channel GXB_SFF_TX[1](n) is assigned to location PIN_N1, channel oPcieTx(n) is assigned to location PIN_Y3, however channels with different reconfiguration controllers cannot be placed in the same channel triplet. Modify your design so the two channels share the same reconfigure controller.

Is there a workaround for this error, when I have no place in the other triplet left ?

kind regards,
Martin

[Harshx]

Hi,

Thanks for contacting Intel. I'm assigned to support request.

I'll investigate on this case and get back to you soon once I have any finding.

Meanwhile can I check with you on:

1. Quartus version you are using?
2. Are you able to share your design or something with we can regenerate the same error?

Thanks for your patience.

Best regards,

Harsh M

[MaHa1]

Dear Harshx,

1. We use: Quartus Prime 18.1.0 Build 625 - Standard Edition

2. I 'm not able share the Design, because of Encrypted Third Party IPs and company knowledge.

When I separated the channels into the other Triplet, I ran into another problem:

Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 Channel PLL(s)).

In the Transceiver Manual I found the Note, that for Full-Duplex communication, the Tx-path needs a CMU PLL which are sourced from channel PLL 1 and 4 in Cyclone V GX.

The only setup where the fitter can place was by only using 2 out of 4 SerDes transceiver channels.

Chip-Planner 5CGXFC7C6U19I7:

So, currently 3 of 6 transceivers are used that the fitter can place the channels.

We need 2 additional SerDes transceiver channels for our design, this would be 5/6 transceivers.

→ Is there a Solution to use PCIe hard IP with more than 2 SerDes Transceivers?

kind regards,
Martin Haiden

[Ash_R_Intel]

Hi,

These issues could be due to the way you have split up your reconfiguration controller, where the minimum "granularity" is a triplet, or perhaps the channel placement is constrained because you are using CMU PLLs, which can only be placed in CH1 or CH4 of a 6-pack.

I believe that you should check the clock sharing and the data rates that you are targeting within a bank. Please check the PLL sharing guidelines: 1.5. PLL Sharing

Regards