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PCIe hard IP endpoint with hpg_ctrler signal

Altera_Forum
Honored Contributor II
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Hi, 

 

I'm using QuartusII 13.0.0.156, and have instantiated a PCIe 4x Hard IP block in endpoint mode for a CycloneIV. 

 

The generated VHDL includes a "hpg_ctrler" port, which, according to the documentation and common sense, should not exist in endpoint mode. Am I missing something obvious here? 

 

Simon
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