PCIe or Rapid Serial IO: Which is easier to implement?

[Altera_Forum]

Hello, I need to choose a high-speed link from my FPGA to a DSP. The DSP has integrated PCIe and Rapid Serial IO. Can anyone tell me which protocol is easier to implement on an Stratix IV or high FPGA? Also, I do not want to use a soft-core processor. If anyone has experience with either or both please let me know your thoughts. 

 Thanks, joe

[Altera_Forum]

I'm also interested in this but on Cyclone IV or Cyclone V. I need connect two FPGAs with serial link up to 3 Gbps. I'm independent on the protocol but I need help with initialization of the transceiver. Has anybody some instalation manual (step by step)? 

 Thanks, Milan

[Altera_Forum]

PCIe protocol implemetation requires a rootport and a endpoint, normally a CPU will acts as rootport, while the FPGA at another end will acts as endpoint. 

A software driver at host side may also required to perform the data transfer. PCIe gen1 is 2.5Gbps, Gen2 is 5.0Gbps.  For Serial Rapid IO, it supports 1x and 4x serial PHY, speed is either 1.25, 2.5, 3.125, and 5.0 Gbps. In your case, it seems like using Rapid IO is more appropriate compare to PCIe. See attached Rapid IO system diagram.