FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5988 Discussions

PCIe problem with large TLPs

Honored Contributor II

I'm sending a TLP (from the application layer) of 4 headers and 128 bits of data (Avalon-TX 128). 


Headers look like this: 


header0 = 32'h60000004; //fmt = 3, length = 4 DW 

header1 = 32'h000000FF; //first BE = F, last BE = F 

header2 = 32'h00000000;  

header3 = address; //that is 32-bit wide 


Afterwars I send it like this: 


tx_valid_next = 1; 

tx_data_next = {header3, header2, header1, header0}; 

tx_sop_next = 1; 


Next cycle: sending the data 

tx_sop_next = 0; 

tx_valid_next = 1; 

tx_data_next = data; //that is 128-bit wide 

tx_eop_next = 1; 


Next cycle: deasserting eop and valid. Also checking TX_ready before asserting TX_valid. 




When I use shmem_display, it shows all zeros, whereas it all works fine with the code like this: 


//3 DW headers, 32-bit data payload, single transaction 

header0 = 32'h40000001; 

header1 = 32'h0000000F;  

header2 = address;  


tx_valid_next = 1; 

tx_data_next = {data, header2, header1, header0};  

tx_sop_next = 1; 

tx_eop_next = 1; 



What am I missing?
0 Kudos
2 Replies
Honored Contributor II

The PCIe spec says: 



--- Quote Start ---  

• For Addresses below 4 GB, Requesters must use the 32-bit format. 

--- Quote End ---  

So, in your TLP generator you have to check the upper 32 bits of the address to be zero and use a 3 word TLP in this case.
Honored Contributor II

It worked with 3DW headers! Thanks!