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PCS configuration error, need help :(

Altera_Forum
Honored Contributor II
806 Views

Hi, my design is getting below errors when doing "Partition Merge" stage. 

 

I am using Terasic DE-5 Net Development Kit which contains Stratix V FPGA Board(5SGXEA7N2F45C2). 

Below errors occur when I give clock signal to Altera Partial Reconfiguration IP (alt_pr). 

 

Error goes off when I give "0" value as a clock to PR IP, but then the DMA module does not work (Of course PR does not work too). 

 

I am struggling with this issue for a long time but couldn't solve it yet. 

Any help would be much appreciated. 

 

 

 

--- Quote Start ---  

 

Error: The selected PCS configuration is illegal. Verify that the protocol_mode, pma_width, byte (de)serializer enabled, latency are all set to valid values. 

Info: No legal values found 

Error: Clock Divider Parameter 'data_rate' is set to an illegal value of '5000000000 bps'. The value is illegal for protocol mode: 'pipe_g3' with a device speed grade of '2_H2', PMA WIDTH of 'ten_bit' and byte serializer mode : 'en_bs_by_4' and latency 'dis_pcs_bypass' on atom'system:system|system_pcieddr:pcieddr|altpcie_256_hip_avmm_hwtcl:pcie_256_dma|altpcie_sv_hip_ast_hwtcl:altera_s5_a2p|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pma:inst_sv_pma|sv_tx_pma:tx_pma.sv_tx_pma_inst|sv_tx_pma_ch:tx_pma_insts[0].sv_tx_pma_ch_inst|tx_pma_ch.tx_cgb'. 

Info: No legal values found 

Error: The selected PCS configuration is illegal. Verify that the protocol_mode, pma_width, byte (de)serializer enabled, latency are all set to valid values. 

Info: No legal values found 

Error: Clock Divider Parameter 'data_rate' is set to an illegal value of '5000000000 bps'. The value is illegal for protocol mode: 'pipe_g3' with a device speed grade of '2_H2', PMA WIDTH of 'ten_bit' and byte serializer mode : 'en_bs_by_4' and latency 'dis_pcs_bypass' on atom'system:system|system_pcieddr:pcieddr|altpcie_256_hip_avmm_hwtcl:pcie_256_dma|altpcie_sv_hip_ast_hwtcl:altera_s5_a2p|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pma:inst_sv_pma|sv_tx_pma:tx_pma.sv_tx_pma_inst|sv_tx_pma_ch:tx_pma_insts[1].sv_tx_pma_ch_inst|tx_pma_ch.tx_cgb'. 

Info: No legal values found 

Error: The selected PCS configuration is illegal. Verify that the protocol_mode, pma_width, byte (de)serializer enabled, latency are all set to valid values. 

Info: No legal values found 

Error: Clock Divider Parameter 'data_rate' is set to an illegal value of '5000000000 bps'. The value is illegal for protocol mode: 'pipe_g3' with a device speed grade of '2_H2', PMA WIDTH of 'ten_bit' and byte serializer mode : 'en_bs_by_4' and latency 'dis_pcs_bypass' on atom'system:system|system_pcieddr:pcieddr|altpcie_256_hip_avmm_hwtcl:pcie_256_dma|altpcie_sv_hip_ast_hwtcl:altera_s5_a2p|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pma:inst_sv_pma|sv_tx_pma:tx_pma.sv_tx_pma_inst|sv_tx_pma_ch:tx_pma_insts[2].sv_tx_pma_ch_inst|tx_pma_ch.tx_cgb'. 

Info: No legal values found 

Error: The selected PCS configuration is illegal. Verify that the protocol_mode, pma_width, byte (de)serializer enabled, latency are all set to valid values. 

Info: No legal values found 

Error: Clock Divider Parameter 'data_rate' is set to an illegal value of '5000000000 bps'. The value is illegal for protocol mode: 'pipe_g3' with a device speed grade of '2_H2', PMA WIDTH of 'ten_bit' and byte serializer mode : 'en_bs_by_4' and latency 'dis_pcs_bypass' on atom'system:system|system_pcieddr:pcieddr|altpcie_256_hip_avmm_hwtcl:pcie_256_dma|altpcie_sv_hip_ast_hwtcl:altera_s5_a2p|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pma:inst_sv_pma|sv_tx_pma:tx_pma.sv_tx_pma_inst|sv_tx_pma_ch:tx_pma_insts[3].sv_tx_pma_ch_inst|tx_pma_ch.tx_cgb'. 

Info: No legal values found 

Error: The selected PCS configuration is illegal. Verify that the protocol_mode, pma_width, byte (de)serializer enabled, latency are all set to valid values. 

Info: No legal values found 

Error: Clock Divider Parameter 'data_rate' is set to an illegal value of '5000000000 bps'. The value is illegal for protocol mode: 'pipe_g3' with a device speed grade of '2_H2', PMA WIDTH of 'ten_bit' and byte serializer mode : 'en_bs_by_4' and latency 'dis_pcs_bypass' on atom'system:system|system_pcieddr:pcieddr|altpcie_256_hip_avmm_hwtcl:pcie_256_dma|altpcie_sv_hip_ast_hwtcl:altera_s5_a2p|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pma:inst_sv_pma|sv_tx_pma:tx_pma.sv_tx_pma_inst|sv_tx_pma_ch:tx_pma_insts[5].sv_tx_pma_ch_inst|tx_pma_ch.tx_cgb'. 

Info: No legal values found 

Error: The selected PCS configuration is illegal. Verify that the protocol_mode, pma_width, byte (de)serializer enabled, latency are all set to valid values. 

Info: No legal values found 

Error: Clock Divider Parameter 'data_rate' is set to an illegal value of '5000000000 bps'. The value is illegal for protocol mode: 'pipe_g3' with a device speed grade of '2_H2', PMA WIDTH of 'ten_bit' and byte serializer mode : 'en_bs_by_4' and latency 'dis_pcs_bypass' on atom'system:system|system_pcieddr:pcieddr|altpcie_256_hip_avmm_hwtcl:pcie_256_dma|altpcie_sv_hip_ast_hwtcl:altera_s5_a2p|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pma:inst_sv_pma|sv_tx_pma:tx_pma.sv_tx_pma_inst|sv_tx_pma_ch:tx_pma_insts[6].sv_tx_pma_ch_inst|tx_pma_ch.tx_cgb'. 

Info: No legal values found 

Error: The selected PCS configuration is illegal. Verify that the protocol_mode, pma_width, byte (de)serializer enabled, latency are all set to valid values. 

Info: No legal values found 

Error: Clock Divider Parameter 'data_rate' is set to an illegal value of '5000000000 bps'. The value is illegal for protocol mode: 'pipe_g3' with a device speed grade of '2_H2', PMA WIDTH of 'ten_bit' and byte serializer mode : 'en_bs_by_4' and latency 'dis_pcs_bypass' on atom'system:system|system_pcieddr:pcieddr|altpcie_256_hip_avmm_hwtcl:pcie_256_dma|altpcie_sv_hip_ast_hwtcl:altera_s5_a2p|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pma:inst_sv_pma|sv_tx_pma:tx_pma.sv_tx_pma_inst|sv_tx_pma_ch:tx_pma_insts[7].sv_tx_pma_ch_inst|tx_pma_ch.tx_cgb'. 

Info: No legal values found 

Error: The selected PCS configuration is illegal. Verify that the protocol_mode, pma_width, byte (de)serializer enabled, latency are all set to valid values. 

Info: No legal values found 

Error: Clock Divider Parameter 'data_rate' is set to an illegal value of '5000000000 bps'. The value is illegal for protocol mode: 'pipe_g3' with a device speed grade of '2_H2', PMA WIDTH of 'ten_bit' and byte serializer mode : 'en_bs_by_4' and latency 'dis_pcs_bypass' on atom'system:system|system_pcieddr:pcieddr|altpcie_256_hip_avmm_hwtcl:pcie_256_dma|altpcie_sv_hip_ast_hwtcl:altera_s5_a2p|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pma:inst_sv_pma|sv_tx_pma:tx_pma.sv_tx_pma_inst|sv_tx_pma_ch:tx_pma_insts[8].sv_tx_pma_ch_inst|tx_pma_ch.tx_cgb'. 

Info: No legal values found 

 

--- Quote End ---  

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