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Altera_Forum
Honored Contributor I
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PIO Core initialization value and pin output

I have a design which uses the Arria II GX and have used Qsys and Quartus v 11.1 SP2 to implement a design that, in part, utilizes a PIO component. I have initialized all the pins to outputs only and have set some bits in the PIO register high, and some bits in the PIO register low. The PIO register bits are directly connected from the Qsys 'system' item to pins on the design. I am noticing that the pins that are associated with the bits that have been set high will appear as logic low for approximately 2.5ms after the chip emerges from reset (pins have been set to HI-Z) and then programmed at startup using a Serial PROM. After the approx 2.5ms of logic low, the pins that have been requested to be set high, will be set to logic high, as requested by the initialization value configured in the PIO core. The pins are connected to an opto-isolator which provide control to my system. 

 

I have some questions regarding this: 

 

- Is this normal? 

- Is this input clock related? The clock that the PIO core is running on is operating at 125MHz. 

- Is this related to any bank settings? I don't have the ability to change the bits on the banks and determine this on my design. 

- Is there something I have missed in the configuration of the device? 

 

I can appreciate that the pins are going to be HI-Z during programming and initial power up and my design is configured for this. However, dependencies on the logic levels that the pins provide control of items within the system that cannot ignore any ambiguity. 

 

Thank you for your assistance. I hope that I have provided enough information on this, but can answer any other questions that will facilitate an answer. I have to believe that others have noticed this as well, however I don't see anything posted in the forums regarding this type of issue. 

 

Steven Balick 

Senior System Engineer 

PV Labs USA
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Altera_Forum
Honored Contributor I
54 Views

I'm not 100% but I think this behaviour is pretty normal. 

PIO status is 'low' at reset and then it is controlled by an Avalon MM master (usually Nios), so it will not reach the required 'high' until the master has completed the reset sequence (in the Nios case, until it has reached the set-PIO-bits instruction) 

I can't remember if Qsys lets you to specify a reset pio status. If not you can use one of these workarounds: 

- if this is a bidir PIO, initialize it as 'all inputs', then set each pin function in software. after it has been assigned a known state 

- tristate the fpga pins driven by PIO with a master_pio_enable signal, so you drive the opto isolators only when you are sure everything inside fpga has started
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