Parallel Flash Loader (PFL) IP Core Signals

[Altera_Forum]

Hallo 

 I am making a PFL IP core for a MAX V CPLD. When i look at the user guide on the following link  https://www.altera.com/documentation/sss1411439280066.html#sss1458191622012  there is the following signal pfl_nreconfigure which is an input and has the following description  After pfl_nreset asserted high for at least fifteen clock cycles, the subsequent low signal at this pin initiates the FPGA reconfiguration. For more flexibility in controlling the FPGA reconfiguration, you can reconnect this pin to a switch to set this input pin high or low. When FPGA reconfiguration is initiated, the fpga_nconfig pin is pulled low to reset the FPGA device. The pfl_clk pin registers this signal. This pins are not available for the flash programming option in the PFL IP core.  But when i generate the PFL IP Core from ALTERA Quartus IP core, i dont see this signal. How can i access this signal or is it necessary???

[Altera_Forum]

Did you enable the parameter for it in the parameter editor? Page 40 of the PDF says the parameter is named "Include input to force reconfiguration".

[Altera_Forum]

Dear sstrell 

 thanks again for your quick and perfect answer. Another signal that is making me confused is the fpga_init_done signal from the following pdf  https://www.altera.com/en_us/pdfs/literature/wp/wp_max_flash.pdf  But i could not find this signal in PFL IP core user guide. So i am bit confused about this signal also.

[Altera_Forum]

That's a really old document. It's named fpga_conf_done in the PFL IP user guide.

[Altera_Forum]

thanks again, now we have to make a custom hardware to test the PFL IP, with MAX V , Cyclone IV E and Micron CFI parallel flash 

then i guess i will again have questions.