Pcie Address problems

[Altera_Forum]

I'm running the PCIE to external memory design(an431) on the cyclone 4 starter kit, and I'm confused with some address issues. 

 1. From the Qsys design, I can see the onchip mem start from address 0x7000000 at Bar0, but I found that address 0 of Bar0 also point to the start address of the onchip mem, e.g. if I write 0xabcd to address 0 of Bar0, I can read the 0xabcd out from address 0x7000000, how is that?  2. We can see in the PCIE ip that every Bar have an avalon base address, when and how will we use that base address?  3. I'm using the example c code from jungo windriver to try the dma function, and when the example alloc the buffer on the host side it uses option DMA_KBUF_BELOW_16M, which means the physical memory of buffer will be under 16M. I get that the PCIE ip can handle buffer no larger than 16M because of the page size and the page count, but I can not see why the address have to be smaller than 16M boundary. I hope that the PCIE ip could visit any address of the host ram, can I achieve that and how?  Thank you very much.

[Altera_Forum]

When an Avalon master access is done for a PCIe slave access the high address bits depend on the BAR, the low address bits come from the PCIe address. 

The way PCIe BARs are setup by sopc is confusing since it tries to hide this - so digs itself into a hole, dunno if qsys is any better.

[Altera_Forum]

Hi,  

 Isn't it BAR would act as address translation between your physical address and pcie address?  So, 0x0 --> 0x7  ??