FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
6673 Discussions

Problem enabling In-system memory editor

Altera_Forum
Honored Contributor II
‎05-17-2015 10:27 PM
2,146 Views

Hi, 

 

As seen in the attached screen shot i am unable to to click the box which would enable the In-system memory editor. 

Please let me know what has to be done to enable the same 

 

 

Thanks, 

Nad
Preview file
21 KB
0 Kudos

Link Copied

1 Reply
Altera_Forum
Honored Contributor II
‎05-17-2015 11:28 PM
1,438 Views

Guys it seems to enable the In-system memory editor the read and write have to have a single clock!

0 Kudos
Copy link
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.