Problems with FFT Testbench

Altera_Forum · ‎02-24-2012

Hi All,

I'm relatively new to FPGA programming, and as a part of a larger project, I am designing a FFT hardware solution to convert a live audio signal into frequency and amplitude pairs (but that's much farther down the road!).

The problem I am having at the minute is with the FFT core itself, namely testing the generated core using ModelSim v.10.0c. I've read the entity into a simulation, but when run, it only takes in the first value from the fft_real_input and fft_imag_input text files. I've included a screenshot of the waveforms that I'm getting.

Any advice you can offer on this would be much appreciated, I'm completely stuck!

Altera_Forum · ‎02-24-2012

Hey, it seems like your troubles are not so hard..

I noticed that sink_sop is always high. It must be asserted only for one cycle, the cycle you provide the 1st input to the fft. Then during the last input you also assert sink_eop, which seems to be always low. Keep both signals low else.

Hope it helps..

Altera_Forum · ‎02-25-2012

Hi,

My testbench does include this function, I've attached the testbench file, but the relevant code sections are as follows:


  //sop and eop asserted in first and last sample of data
  always @ (posedge clk)
  begin
    if (reset_n == 1'b0)
      cnt <= 0;
    else
      begin
        if (sink_valid == 1'b1 & sink_ready == 1'b1)
	  begin
             if (cnt == fftpts_array - 1)
               cnt <= 0;
             else
               cnt <= cnt + 1;
          end
      end
  end

and


   // generate start and end of packet signals
   assign sink_sop = (cnt == 0) ? 1'b1 : 1'b0 ;
   assign sink_eop = ( cnt == fftpts_array - 1 ) ? 1'b1 : 1'b0;

Altera_Forum · ‎02-25-2012

UPDATE

I've sorted that problem I was having, turned out the Testbench .v file missed out any instance of setting sink_ready to 1.

So at the moment, all the input processes are working fine. The testbench runs for 4 frames of random real and imaginary input data, read from respective text files.

...and that's as far as it gets.

I'm currently not getting any output from the instantiated FFT module, either as a wave form or in the file on disk.

Any ideas?

Altera_Forum · ‎02-25-2012

Hey,

have in mind that sink_ready is an output signal, you don't have to assert/deassert it, but just read its value so as to be sure that FFT can accept new inputs.

Also check if source_ready (which is an input signal to the FFT) is asserted when FFT is supposed to output its result..

Altera_Forum · ‎02-26-2012

Ah see I asserted sink_ready in my testbench code in order to get the input side working. Without it I was getting nothing beyond the first value, so I guess something's causing both of those problems. Any ideas on how to fix it? I've spent hours on it now and am getting absolutely nowhere!

Altera_Forum · ‎02-27-2012

Hi,

sink_ready is an output signal of the FFT function. I don't know why you think things work better when you force a value to it. What I know is that you should only read the value of this signal, in order to know if FFT is ready to accept new input data. You initiate the input data transfer by just asserting the sink_valid signal. When both sink_ready and sink_valid are asserted and you also assert sik_sop for one cycle the FFT can start fetching the inputs.

Providing some more details would also be useful.