FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6227 Discussions

Problems with the Test Pattern Generator

Honored Contributor II


I'm trying to set up a Test Pattern Generator from the VIP. 

I'm using a Cyclone III Development Board with DVI adapter. 

My problem is, that the monitor shows no pattern. 

The resolution is 1680x1050. 

I used the following settings: 

External PLL Clock: 119MHz 

Hor Blank: 160px 

Hor Sync: 32px 

Hor Front Porch: 48px 

Hor Back Porch: 80px 

Ver Blank: 30lines 

Ver Sync: 6lines 

Ver Front Porch: 3lines 

Ver Back porch: 21lines 

I take a few pictures and attached them to my post. 


Hope somebody can help me. 


Thank you!
0 Kudos
1 Reply
Honored Contributor II

Hello again, 

in the meantime, i tried another system unseccesfully. 

In Qsys I took a Clocked Video Input and gave it on a Clocked Video Output, so that i get a loop through. For the settings I take the DVI 1080p60 presets. 

The Video Clock comes from a PLL and the System Clock is 125MHz from Y4. 

Anyway I don't get any picture out of my DVI port =( 

Besides I measured with a scope at measuring point V on the Bitec DVI Card. 

On the input site, I could see a vertical sync signal. On the output site was nothing... 

Now I thing that I have overlook something on the board. 


Thanks for help!
0 Kudos