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Q20.2: Critical Warning (19166): For IOPLL feedback delay chain setting was reduced from "X" to "0"

JMiret
Novice
317 Views

Quartus Prime
Version 20.2.0 Build 50 06/11/2020 SC Pro Edition
Copyright (C) 2020  Intel Corporation. All rights reserved.

 

Target FPGAs:

"1SX280HU2F50E1VGAS"
"1SX280HU1F50E2VG"

"1SX280HU3F50E2VG"


When compiling a design using Quartus 20.2 that uses the JESD204B IP, I've created a PLL to provide the Link Clock which is to be fed to the JESD204B IP. However, when specifying the Link Clock PLL to be used in "Normal" mode vs. "Direct" mode, we now get some Critical Warnings.

 

The documentation indicates that this link clock needs to be set to "normal" to get deterministic latencies and to support sysref sampling.

This Link Clock is then distributed to four Tx and four Rx JESD 204B IP instantiations.

 

Since making this change, we're seeing a number of these errors, in the form of:

 

Critical Warning (19166): For IOPLL "jesd_pll[3].jesd_core_pll_inst_250|iopll_0|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll", feedback delay chain setting was reduced from "4497" to "3843" to keep the IOPLL stable.

 

Critical Warning (19166): For IOPLL "jesd_pll[0].jesd_core_pll_inst_250|iopll_0|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll", feedback delay chain setting was reduced from "3524" to "0" to keep the IOPLL stable.                                                      
Critical Warning (19166): For IOPLL "jesd_pll[2].jesd_core_pll_inst_250|iopll_0|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll", feedback delay chain setting was reduced from "3808" to "65" to keep the IOPLL stable.                                                     
Critical Warning (19166): For IOPLL "jesd_pll[3].jesd_core_pll_inst_250|iopll_0|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll", feedback delay chain setting was reduced from "5217" to "0" to keep the IOPLL stable.                                                      
Critical Warning (19166): For IOPLL "jesd_pll[1].jesd_core_pll_inst_250|iopll_0|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll", feedback delay chain setting was reduced from "2790" to "125" to keep the IOPLL stable.                                                   
Critical Warning (19166): For IOPLL "jesd_pll[0].jesd_core_pll_inst_250|iopll_0|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll", feedback delay chain setting was reduced from "3524" to "0" to keep the IOPLL stable.                                                      
Critical Warning (19166): For IOPLL "jesd_pll[2].jesd_core_pll_inst_250|iopll_0|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll", feedback delay chain setting was reduced from "3808" to "65" to keep the IOPLL stable.                                                     
Critical Warning (19166): For IOPLL "jesd_pll[3].jesd_core_pll_inst_250|iopll_0|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll", feedback delay chain setting was reduced from "5217" to "0" to keep the IOPLL stable.                                                      
Critical Warning (19166): For IOPLL "jesd_pll[1].jesd_core_pll_inst_250|iopll_0|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll", feedback delay chain setting was reduced from "2790" to "125" to keep the IOPLL stable.                                                   
Critical Warning (19166): For IOPLL "jesd_pll[0].jesd_core_pll_inst_250|iopll_0|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll", feedback delay chain setting was reduced from "3524" to "0" to keep the IOPLL stable.                                                      
Critical Warning (19166): For IOPLL "jesd_pll[2].jesd_core_pll_inst_250|iopll_0|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll", feedback delay chain setting was reduced from "3758" to "10" to keep the IOPLL stable.                                                     
Critical Warning (19166): For IOPLL "jesd_pll[3].jesd_core_pll_inst_250|iopll_0|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll", feedback delay chain setting was reduced from "5280" to "0" to keep the IOPLL stable.


Critical Warning (19166): For IOPLL "jesd_pll[1].jesd_core_pll_inst_250|iopll_0|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll", feedback delay chain setting was reduced from "2689" to "16" to keep the IOPLL stable.


However, I don't see any documentation on what this means, or why it's happening.

 

The relevant PLL instantiation block looks like this, and is within a generate block:

 

 jesd_core_pll_250 jesd_core_pll_inst_250 (
     .rst      (w_JesdCorePllReset   [genvar_JESD]), //          input
     .refclk   (w_JesdDevClk         [genvar_JESD]), // 250MHz   input
     .locked   (w_JesdCorePllLocked_250  [genvar_JESD]), //         output
     .outclk_0 (w_LinkClk_250        [genvar_JESD])  // 250MHz  output TX & RX 1GSPS
 );

 jesd_core_pll_300 jesd_core_pll_inst_300 (
     .rst      (w_JesdCorePllReset   [genvar_JESD]), //          input
     .refclk   (w_JesdDevClk         [genvar_JESD]), // 250MHz   input
     .locked   (w_JesdCorePllLocked_300  [genvar_JESD]), //         output
     .outclk_0 (w_LinkClk_300        [genvar_JESD])  // 300MHz  output JESD RX 3GSPS
 );

 jesd_core_pll_375 jesd_core_pll_inst_375 (
     .rst      (w_JesdCorePllReset   [genvar_JESD]), //          input
     .refclk   (w_JesdDevClk         [genvar_JESD]), // 250MHz   input
     .locked   (w_JesdCorePllLocked_375  [genvar_JESD]), //         output
     .outclk_0 (w_LinkClk_375        [genvar_JESD])  // 375MHz  output JESD TX 3GSPS
 );


 assign w_JesdLinkClk_RX[genvar_JESD] = ((JESD_L == 4) && (JESD_M == 2) && (JESD_F == 1) && (JESD_S ==  1)) ?    w_LinkClk_250[genvar_JESD] :
                                     /* ((JESD_L ==  && (JESD_M == 2) && (JESD_F ==  && (JESD_S == 20)) ? */ w_LinkClk_300[genvar_JESD] ;

 assign w_JesdLinkClk_TX[genvar_JESD] = ((JESD_L == 4) && (JESD_M == 2) && (JESD_F == 1) && (JESD_S ==  1)) ?    w_LinkClk_250[genvar_JESD] :
                                     /* ((JESD_L ==  && (JESD_M == 2) && (JESD_F ==  && (JESD_S == 20)) ? */ w_LinkClk_375[genvar_JESD] ;

 //For JESD_Rx
 assign w_JesdCorePllLocked[genvar_JESD+4] = ((JESD_L == 4) && (JESD_M == 2) && (JESD_F == 1) && (JESD_S ==  1)) ?    w_JesdCorePllLocked_250[genvar_JESD] :
                                     /* ((JESD_L ==  && (JESD_M == 2) && (JESD_F ==  && (JESD_S == 20)) ? */      w_JesdCorePllLocked_300[genvar_JESD] ;
 //For JESD_Tx
 assign w_JesdCorePllLocked[genvar_JESD+8] = ((JESD_L == 4) && (JESD_M == 2) && (JESD_F == 1) && (JESD_S ==  1)) ?    w_JesdCorePllLocked_250[genvar_JESD] :
                                     /* ((JESD_L ==  && (JESD_M == 2) && (JESD_F ==  && (JESD_S == 20)) ? */      w_JesdCorePllLocked_375[genvar_JESD];

 assign w_JesdLinkClk_RX         [genvar_JESD+4] = w_JesdLinkClk_RX   [genvar_JESD];
 //assign w_JesdLinkClk_TX         [genvar_JESD+4] = w_JesdLinkClk_TX   [genvar_JESD]; UNCOMMENT WHEN 8 TX

 

The idea is that the PLLs which we aren't going to use will by synthesized away, which is happening. But I have no idea what this error means, or how to fix it.

 

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3 Replies
Ash_R_Intel
Employee
282 Views

Hi,

This warning occur due to reason specified in the following link:

https://www.intel.com/content/www/us/en/programmable/quartushelp/20.2/index.htm#msgs/msgs/wfitcc_fit...


Please note the difference between the two modes:

• Direct mode—the PLL minimizes the feedback path length to produce the smallest possible jitter at the PLL output. In this mode, the PLL does not compensate for any clock networks.

• Normal mode—the PLL feedback path source is a global or regional clock network, minimizing clock delay from the input clock pin to the core registers through global or regional clock network.


As Direct mode does not have any feedback path, the warning will not occur for that mode. It make sense only for the Normal mode. Action to be taken as specified in the above link.


Regards


JMiret
Novice
276 Views

Hi,

 

Thanks for the reference. However, I'm a bit confused as to the best way to reduce the feedback path length: how is that calculated, and what do I need to do in order to reduce it? We're connecting the PLL to the IP and our user logic. Should we be using a different clock for our user logic?

More specifically, what is the proceedure for determining the length of the feedback path, and how does one reduce the feedback path length?

 

 

Ash_R_Intel
Employee
129 Views

One way is to reduce the fanout of the PLL output clock.


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