QSYS throws error when generating DDR2 UniPHY RAM

[DSold3]

Hi,

I'm geting this error while generating a Nios II system with JTAG and DDR2 UniPHY ram (EMIF enabled on JTAG).

Quartus Prime Standard is version 16.1.2 build 203.

Wasn't happening with Quartus 16.1.0.

Error: p0: add_fileset_file: No such file /tmp/alt8046_7281660134323950256.dir/0006_p0_gen/core_ddr_ddr2_p0_clock_pair_generator.v

   while executing

"add_fileset_file $file_name [::alt_mem_if::util::hwtcl_utils::get_file_type $file_name 0] PATH $generated_file"

   ("foreach" body line 4)

   invoked from within

"foreach generated_file [generate_verilog_fileset $name $tmpdir QUARTUS_SYNTH] {

      set file_name [file tail $generated_file]

      _dprint 1 "Preparing to ..."

   (procedure "generate_synth" line 7)

   invoked from within

"generate_synth core_ddr_ddr2_p0"

[sstrell]

Since you say you've previously successfully generated this system, I'd try trashing the directory that was previously generated (named after your .qsys file). That directory is usually overwritten when you regenerate a system, but it can't hurt to try.

Other than that, have you made any other changes to anything, like move the project files to a different location or anything else?

#iwork4intel

[Kenny_Tan]

You also can try on the latest one Q18.1.1.

[DSold3]

In 18.1.1 no issues with the compiler. It seems to be an error in Qsys 16.1.1