Qsys PCIe core fails timing

[Altera_Forum]

Hi, 

 I've been analyzing the Altera PCIe Hard-IP cores. I started off with the Qsys PCIe code, since it had the simplest interface.  Here's the test setup:  * Quartus 11.0, 11.1sp1, 11.1sp2 * Cyclone IV GX Transceiver Starter Kit  - x1 PCIe end-point with 125Mhz application clock  - x1 PCIe end-point with 62.5MHz application clock * Stratix IV GX Development Kit  - x8 PCIe end-point with 250Mhz application clock  - x4 PCIe end-point with 125Mhz application clock  The Qsys designs are similar to the example provided in the PCIe Compiler Users Guide.  I've described the design process and have written automated synthesis scripts (making it easy for anyone to reproduce my results):  http://www.ovro.caltech.edu/~dwh/correlator/pdf/altera_pcie_analysis.pdf (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/altera_pcie_analysis.pdf) http://www.ovro.caltech.edu/~dwh/correlator/pdf/altera_pcie.zip (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/altera_pcie.zip)  The Cyclone IV GX designs were failing timing due to the multi-corner timing optimization setting defaulting to off. The designs pass timing for a -6 speed grade device, but fail for -7 speed grade. This is inconsistent with the PCIe Compiler Users Guide.  The Stratix IV GX x8 design still fails timing analysis (ever so slightly). I'm in the process of trying to resolve this via an Altera Service Request. The x4 design has a problem with width negotiation; its sometimes x4, but often x1 or x2, I'm not sure what is wrong.  If anyone wants to try these designs, or has any insight or suggestions on where I may have gone wrong, I'd love to know, thanks!  Cheers, Dave

[Altera_Forum]

--- Quote Start ---   This tells me that the PCIe Hard IP master may have been doing something wierd. And the NIOS II running maybe changed the state of how the Avalon MM interconnect was behaving such that the PCIe Avalon MM master , BAR1, was getting stale data back on reads.   --- Quote End ---   To test your theory, you could try inserting a pipeline bridge between the NIOS II and the PCIe. The bridge would be pointless, but it might change the Avalon-MM internal pipelining sufficiently to "change" your error.  Cheers, Dave

[Altera_Forum]

Hi Dave 

 I am a new guy for pcie design, so i downlaod your proejct and file! But i need your help! how can i open the qsys file in version Quartus Prime v17, it's seem not work!  Thanks  Br. Benson