Qsys won't generate testbench with VHDL 'application' source...

[Altera_Forum]

As described here.... 

 http://www.alteraforum.com/forum/showthread.php?t=31416  .. I have a system that I'm trying to get working with the CycloneIV hard PCIe interface.  This is a system that works well with the Altera PCI IP on a Cyclone III so I thought the transfer to a PCIe interface would be fairly smooth.  Unfortunately the PCIe based system isn't working so I want to simulate it to see what's happening, but Qsys is erroring on testbanch generation because my application is written in VHDL.   Has anyone else seen this problem?  Is there a way round it?  Thanks for any pointers,  Nial.

[Altera_Forum]

Hi, yes I saw the same things on Stratix IV. 

The problem is the PCIE macro that at the moment has not the code in vhdl.  The only solution is to generate the simulation in verilog (so if you've some custom components in qsys written in vhdl, you've to translate it in verilog for the simulation porpouse).  Note that you can add more sources as component files. For example you could add a .vhd files used for synthesys and simulation and a verilog file used only in the simulation. Doing this, when you later compile your project in quartus you use your vhdl file, whereas when in Qsys you generate the simulation files it chose the correct file depending on the setting of the simulation (verilog or vhdl).

[Altera_Forum]

--- Quote Start ---  The only solution is to generate the simulation in verilog (so if you've some custom components in qsys written in vhdl, you've to translate it in verilog for the simulation porpouse).  --- Quote End ---    It can not be the case that if we prefer to write VHDL code, that we have to manually code the same functionality in verilog, just to be able to simulate a Qsys system?

[Altera_Forum]

--- Quote Start ---  Hi, yes I saw the same things on Stratix IV. The problem is the PCIE macro that at the moment has not the code in vhdl.   The only solution is to generate the simulation in verilog (so if you've some custom components in qsys written in vhdl, you've to translate it in verilog for the simulation porpouse).   Note that you can add more sources as component files. For example you could add a .vhd files used for synthesys and simulation and a verilog file used only in the simulation. Doing this, when you later compile your project in quartus you use your vhdl file, whereas when in Qsys you generate the simulation files it chose the correct file depending on the setting of the simulation (verilog or vhdl).  --- Quote End ---     From what I understand you're saying Josyb is correct, this is madness.   I have access to a mixed language simulator, I don't give a toss what the  PCIe models are written in, I'm sure I can even hack a verilog tesbench to drive the interface.   I don't even care if there's a verilog wrapper but I _need_ to be able to use my VHDL in a testbench (it's a big design, months of work that I'm _trying_ to transfer from a PCI based interface to PCIe).     Nial

[Altera_Forum]

--- Quote Start ---   I have access to a mixed language simulator, I don't give a toss what the  PCIe models are written in, I'm sure I can even hack a verilog tesbench to drive the interface.   I don't even care if there's a verilog wrapper but I _need_ to be able to use my VHDL in a testbench (it's a big design, months of work that I'm _trying_ to transfer from a PCI based interface to PCIe).    --- Quote End ---  I haven't tried using Qsys for mixed language designs, but I have done this under SOPC Builder. I wanted to use the Avalon-MM BFMs, which are only supplied in SystemVerilog, and only useable from SystemVerilog.  The SystemVerilog testbench that is generated under SOPC Builder is pretty brain-dead; just a clock and reset generator and dangling connections.   So I don't even bother clicking the 'generate simulation' check box inside SOPC Builder, I just take the generated files and create my own testbench.  The tricky thing sometimes is to figure out which HDL files are needed for simulation. For that, I just create a very small test design, and I do check the 'generate simulation' and I then look at the 'include statements in the generated files, and the setup_sim.do file.  I then add my VHDL components to the simulation script, and Modelsim is happy to simulate the whole system.  Perhaps that would be a solution for you too.  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  From what I understand you're saying Josyb is correct  --- Quote End ---    I've been told that it something that need to be fixed, but at the moment PCIe is only in verilog so if you've this in Qsys you can generate TestBenches only in verilog.

[Altera_Forum]

--- Quote Start ---  I've been told that it something that need to be fixed, but at the moment PCIe is only in verilog so if you've this in Qsys you can generate TestBenches only in verilog.  --- Quote End ---    I wouldn't be naive. In another thread (http://www.alteraforum.com/forum/showthread.php?t=30879 (http://www.alteraforum.com/forum/showthread.php?t=30879)) BadOmen said Altera is using only Verilog and SystemVerilog for their IP (and examples).  An extract from the MegaCore IP Release Notes and Errata shows it all:   --- Quote Start ---  vhdl example driver fails in simulation The VHDL example driver for designs using the high-performance controller (HPC) fails to simulate. affected configurations This issue affects all ALTMEMPHY-based designs using the high-performance controller, and targeting VHDL. design impact The VHDL example driver fails to compile in VCS/VCSMX and hence cannot simulate. workaround The workaround for this issue is to use the Verilog example driver. solution status this issue will not be fixed.  --- Quote End ---