Quartus 9.1 doesn't inferred RAM

[Altera_Forum]

Hello folks, 

 I'm working on a project that requires large data amount serialization... If I implement this component logic elements based, it consumes lots of valuable resources... so I'm implementing it using memory elements.  I developed a serializator with a customized version of the Altera's design example "ram_dual.vhd".    The main modifications are: - Its output returns only one bit; - There is an input "read_address_pos" which receives the position number of data that will be outputed. So, I need some logic to generate all the memory positions and serialize the bits..   The file can be seen at the attached file "ram_dual_32p1.vhd"...   I was using Quartus 8.1 to synthesize and it was inferring memory bits correctly.. But I migrate the project to Quartus 9.1 sp2 and it's inferring the same vhd source as logic elements. I checked the settings and they are also the same! Am I missing something?   Thanks in advance,   Willian

[Altera_Forum]

Hello,  

 Quartus 9.0 SP2 also infers a memory block from that code. I don't have 9.1 here at hand to test.  Often, Quartus prints out a message explaining why it did not infer RAM blocks for arrays. Can you find such a message in the log?  And by the way, what device family are you targeting?

[Altera_Forum]

Sometimes it only inferrs if the RAM is "Big enough". 

So I suggest you try inferring a bigger one.

[Altera_Forum]

Thanks for your replies.. 

 I also compiled that code in Quartus 9.0 and it infers block memory, as I wish... But in 9.1 version it doesn't infer them... I looked for some message but it just give this message "Info: Implemented 352 logic cells"... My device is an Arria GX EP1AGX35DF780C6.   I also tried to increase the size memory to 512 and 1024 bits, but it still inferring dedicated registers... :(   Any other ideas?   Thanks in advance...   Willian