Quartus_Lite_22_1_not_generating_time_limit_sof

[FPGA70]

I'm resurrecting a Cyclone IV project from a few years back.  The last time I compiled and ran it was with version 20.1.  Within the last week I updated to version 22.1.  I am and have been running the Linux versions of Quartus Lite.

I recreated the project in the latest version in case there were incompatibilities between versions.  I would like to generate the BSP so that I can download some C-code in Eclipse in order to communicate with my PC, but I am running into a problem.

For IP I am using a Nios II/e and a PLL.  Everything compiles fine and a standard .sof is generated, but the time_limit.sof is not generated.

When I look at the 'IP Cores Summary' in 'Analysis & Synthesis' I see 6 instances of Signal Tap which I assume, because it indicates it is licensed, is the cause of Quartus Lite not generating the time_limit.sof.

I have verified that Settings/Signal Tap Logic Analyzer/ DOES NOT have 'Enable Signal Tap Logic Analyzer' checked. Any ideas would be appreciated.

Thanks

[RichardTanSY_Altera]

If the IP has been licensed (not on evaluation license), then the Quartus will generated .sof file.

Why use Time-Limited Programming File when you have the standard .sof file that works without a time limitation?

You can check your IP license status at the assembly report and compare the differences between two projects.

It should show you a list of all the cores that you used that require a license. It should tell you exactly which core you used that made your sof file time limited.

https://www.intel.com/content/www/us/en/docs/programmable/683475/19-4/checking-the-ip-license-status.html

Best Regards,

Richard Tan

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.

[sstrell]

Signal Tap is not a licensed IP so that wouldn't prevent you from getting a .sof file, time-limited or otherwise.  But it doesn't make sense that Signal Tap is disabled and yet you are seeing it.  Are you confusing Signal Tap with something like "sld_hub"?  That's just the JTAG interface for debugging.

I use Pro so the setting may be in a different location, but check that you have .sof file generation (the Assembler) enabled or try running the Assembler manually from the Processing menu to see if it spits out a file.  Also check Assignments -> Device -> Device and Pin Options and Assignments -> Settings -> Assembler.

[FPGA70]

It has been a few years since I ran licensed copies of Vivado or Quartus at work.  These days I run the Lite version of Quartus which works great for my hobby stuff. 

You are right that there was a difference between the project I ran some years back and the one I am trying to get to run under 22.1.  I used Nios II/f then, but I found literature that indicated it was not available for this latest version of Quartus Lite so I am running Nios II/e which works fine for my purposes.  In the past I would see a time-limit.sof generated, but maybe Nios II/e does not do that.  Selecting the Nios II/e compiles with no errors.

The problem I am running into now is that when I try to generate a "Neos II Application and BSP from Template" with Eclipse, it generates 3 errors during Build even when using the standard "hello world small" file.  Guess it is time to go over to the Eclipse forum and bug them.

Thanks for your help

[RichardTanSY_Altera]

I believe that Nios II/e is free to use so that could be why there is no time-limited .sof generated this time.

Please do bug the Nios expert for your follow-up question.  ;  ) 

Anyhow, I’m glad that your question has been addressed, I now transition this thread to community support.

Thank you.

Best Regards,

Richard Tan

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.

[sstrell]

I guess there's a misunderstanding here.  Are you saying you get *no* .sof file or that you do get a .sof file but you expect it to be time-limited?

If you get no .sof file at all, then follow what I said above.  If you are saying you get a .sof but it is not time-limited, that's because II/e does not require a license (as was mentioned) while II/f (which does still exist) does require a license.  It sounds like this is what you mean.

[FPGA70]

Thank you for your response.  After I build the project I get a .sof file, but I expected the time-limited version. 

Speculation:  I had used the Nios II/f in with an earlier version of Quartus Lite (this might have been before Altera was bought by Intel) so I am assuming that Quartus Lite used to generate a time-limited.sof (good for 1 hour). 

Now it is not possible to use the II/f with Lite and generate the time-limited.sof.  This is okay because I am not using the resources supplied beyond the II/e core.  As I mentioned, this is just a hobby now that I am retired and playing mostly with ham radio and trivial projects compared to years back. 

You can close this item, but I do have a question for you.  I downloaded Eclipse Mars.2 Release (4.5.2) but it fails when I try to create the Nios II BSP.  I tried a generic 'Hello World' code with the Nios II BSP, but I still get the same failure report (see attachment).  Is this something for the Intel forum or should I chat with the Eclipse organization?  Searching both sites, I did not find what I thought was a similar problem. 

Last note:  Just before upgrading the Quartus and Eclipse applications, I upgraded to Linux MInt 21.1.

Thanks again.  I appreciate the cycles you have spent on this ticket.

Jim